cvw/pipelined/regression
Ross Thompson 3cc37e3f12 Completely stripped down imperas simulation.
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
2023-01-12 12:48:38 -06:00
..
slack-notifier
wave-dos
buildrootBugFinder.py
fpga-wave.do Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 2022-12-23 15:10:37 -06:00
lint-wally
linux-wave.do Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 2022-12-23 15:10:37 -06:00
make-tests.sh
Makefile
makefile-memfile
regression-wally Moved floating-point tests earlier in Wally config 2022-12-25 22:31:20 -08:00
sim-buildroot
sim-buildroot-batch
sim-testfloat
sim-testfloat-batch
sim-wally
sim-wally-batch
testfloat.do
wally-harvard.do
wally-pipelined-batch.do
wally-pipelined-imperas.do Completely stripped down imperas simulation. 2023-01-12 12:48:38 -06:00
wally-pipelined.do
wave-all.do
wave-fpu.do reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
wave.do Possibly working speculative global history. 2023-01-08 23:46:53 -06:00