forked from Github_Repos/cvw
510 lines
16 KiB
Systemverilog
510 lines
16 KiB
Systemverilog
///////////////////////////////////////////
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// pagetablewalker.sv
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//
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// Written: tfleming@hmc.edu 2 March 2021
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// Modified: kmacsaigoren@hmc.edu 1 June 2021
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// implemented SV48 on top of SV39. This included, adding a level of the FSM for the extra page number segment
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// adding support for terapage encoding, and for setting the TranslationPAdr using the new level,
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// adding the internal SvMode signal
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//
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// Purpose: Page Table Walker
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// Part of the Memory Management Unit (MMU)
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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/* ***
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TO-DO:
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- Implement faults on accessed/dirty behavior
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*/
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module pagetablewalker
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(
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// Control signals
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input logic clk, reset,
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input logic [`XLEN-1:0] SATP_REGW,
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// Signals from TLBs (addresses to translate)
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input logic [`XLEN-1:0] PCF, MemAdrM,
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input logic ITLBMissF, DTLBMissM,
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input logic [1:0] MemRWM,
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// Outputs to the TLBs (PTEs to write)
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output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM,
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output logic [1:0] PageType,
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output logic ITLBWriteF, DTLBWriteM,
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output logic SelPTW,
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// *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU
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input logic [`XLEN-1:0] HPTWReadPTE,
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input logic MMUReady,
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input logic HPTWStall,
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// *** modify to send to LSU
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output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide
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output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide
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output logic HPTWRead,
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// Faults
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output logic WalkerInstrPageFaultF,
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output logic WalkerLoadPageFaultM,
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output logic WalkerStorePageFaultM
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);
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generate
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if (`MEM_VIRTMEM) begin
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// Internal signals
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// register TLBs translation miss requests
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logic ITLBMissFQ, DTLBMissMQ;
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logic [`PPN_BITS-1:0] BasePageTablePPN;
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logic [`XLEN-1:0] TranslationVAdr;
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logic [`XLEN-1:0] CurrentPTE;
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logic [`PA_BITS-1:0] TranslationPAdr;
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logic [`PPN_BITS-1:0] CurrentPPN;
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logic [`SVMODE_BITS-1:0] SvMode;
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logic MemStore;
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// PTE Control Bits
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logic Dirty, Accessed, Global, User,
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Executable, Writable, Readable, Valid;
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// PTE descriptions
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logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE;
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// Outputs of walker
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logic [`XLEN-1:0] PageTableEntry;
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logic StartWalk;
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logic EndWalk;
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typedef enum {LEVEL0_SET_ADRE,
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LEVEL0_WDV,
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LEVEL0,
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LEVEL1_SET_ADRE,
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LEVEL1_WDV,
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LEVEL1,
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LEVEL2_SET_ADRE,
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LEVEL2_WDV,
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LEVEL2,
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LEVEL3_SET_ADRE,
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LEVEL3_WDV,
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LEVEL3,
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LEAF,
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IDLE,
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FAULT} statetype;
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statetype WalkerState, NextWalkerState, PreviousWalkerState;
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logic PRegEn;
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logic SelDataTranslation;
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logic AnyTLBMissM;
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assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
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assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
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assign MemStore = MemRWM[0];
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// Prefer data address translations over instruction address translations
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assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF;
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assign SelDataTranslation = DTLBMissMQ | DTLBMissM;
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flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);
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flopenrc #(2) TLBMissMReg(clk, reset, EndWalk, StartWalk | EndWalk, {DTLBMissM, ITLBMissF}, {DTLBMissMQ, ITLBMissFQ});
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
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flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, CurrentPTE); // Capture page table entry from data cache
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assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
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assign AnyTLBMissM = DTLBMissM | ITLBMissF;
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assign StartWalk = (WalkerState == IDLE) & AnyTLBMissM;
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assign EndWalk = (WalkerState == LEAF) || (WalkerState == FAULT);
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// unswizzle PTE bits
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assign {Dirty, Accessed, Global, User,
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Executable, Writable, Readable, Valid} = CurrentPTE[7:0];
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// Assign PTE descriptors common across all XLEN values
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assign LeafPTE = Executable | Writable | Readable;
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assign ValidPTE = Valid && ~(Writable && ~Readable);
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assign AccessAlert = ~Accessed | (MemStore & ~Dirty);
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// Assign specific outputs to general outputs
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assign PageTableEntryF = PageTableEntry;
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assign PageTableEntryM = PageTableEntry;
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// generate
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if (`XLEN == 32) begin
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logic [9:0] VPN1, VPN0;
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// State transition logic
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always_comb begin
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PRegEn = 1'b0;
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TranslationPAdr = '0;
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HPTWRead = 1'b0;
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PageTableEntry = '0;
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PageType = '0;
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DTLBWriteM = '0;
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ITLBWriteF = '0;
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WalkerInstrPageFaultF = 1'b0;
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WalkerLoadPageFaultM = 1'b0;
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WalkerStorePageFaultM = 1'b0;
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SelPTW = 1'b1;
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case (WalkerState)
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IDLE: begin
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SelPTW = 1'b0;
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if (AnyTLBMissM & SvMode == `SV32) begin
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NextWalkerState = LEVEL1_SET_ADRE;
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end else begin
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NextWalkerState = IDLE;
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end
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end
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LEVEL1_SET_ADRE: begin
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NextWalkerState = LEVEL1_WDV;
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TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
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end
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LEVEL1_WDV: begin
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TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
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HPTWRead = 1'b1;
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if (HPTWStall) begin
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NextWalkerState = LEVEL1_WDV;
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end else begin
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NextWalkerState = LEVEL1;
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PRegEn = 1'b1;
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end
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end
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LEVEL1: begin
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// *** <FUTURE WORK> According to the architecture, we should
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// fault upon finding a superpage that is misaligned or has 0
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// access bit. The following commented line of code is
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// supposed to perform that check. However, it is untested.
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if (ValidPTE && LeafPTE && ~BadMegapage) begin
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NextWalkerState = LEAF;
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TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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end
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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else if (ValidPTE && ~LeafPTE) begin
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NextWalkerState = LEVEL0_SET_ADRE;
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TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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HPTWRead = 1'b1;
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end else begin
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NextWalkerState = FAULT;
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end
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end
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LEVEL0_SET_ADRE: begin
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NextWalkerState = LEVEL0_WDV;
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TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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end
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LEVEL0_WDV: begin
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TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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HPTWRead = 1'b1;
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if (HPTWStall) begin
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NextWalkerState = LEVEL0_WDV;
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end else begin
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NextWalkerState = LEVEL0;
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PRegEn = 1'b1;
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end
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end
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LEVEL0: begin
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if (ValidPTE & LeafPTE & ~AccessAlert) begin
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NextWalkerState = LEAF;
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TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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end else begin
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NextWalkerState = FAULT;
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end
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end
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LEAF: begin
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NextWalkerState = IDLE;
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PageTableEntry = CurrentPTE;
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PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux?
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DTLBWriteM = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
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TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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end
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FAULT: begin
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SelPTW = 1'b0;
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NextWalkerState = IDLE;
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WalkerInstrPageFaultF = ~DTLBMissMQ;
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WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
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WalkerStorePageFaultM = DTLBMissMQ && MemStore;
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end
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// Default case should never happen, but is included for linter.
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default: NextWalkerState = IDLE;
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endcase
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end
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// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
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assign MegapageMisaligned = |(CurrentPPN[9:0]);
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assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
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assign VPN1 = TranslationVAdr[31:22];
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assign VPN0 = TranslationVAdr[21:12];
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// Assign outputs to ahblite
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// *** Currently truncate address to 32 bits. This must be changed if
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// we support larger physical address spaces
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assign HPTWPAdrE = TranslationPAdr[31:0];
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end else begin
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logic [8:0] VPN3, VPN2, VPN1, VPN0;
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logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage;
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always_comb begin
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PRegEn = 1'b0;
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TranslationPAdr = '0;
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HPTWRead = 1'b0;
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PageTableEntry = '0;
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PageType = '0;
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DTLBWriteM = '0;
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ITLBWriteF = '0;
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WalkerInstrPageFaultF = 1'b0;
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WalkerLoadPageFaultM = 1'b0;
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WalkerStorePageFaultM = 1'b0;
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SelPTW = 1'b1;
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case (WalkerState)
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IDLE: begin
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SelPTW = 1'b0;
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if (AnyTLBMissM & SvMode == `SV48) begin
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NextWalkerState = LEVEL3_SET_ADRE;
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end else if (AnyTLBMissM & SvMode == `SV39) begin
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NextWalkerState = LEVEL2_SET_ADRE;
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end else begin
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NextWalkerState = IDLE;
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end
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end
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LEVEL3_SET_ADRE: begin
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NextWalkerState = LEVEL3_WDV;
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TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
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end
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LEVEL3_WDV: begin
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TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
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HPTWRead = 1'b1;
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if (HPTWStall) begin
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NextWalkerState = LEVEL3_WDV;
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end else begin
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NextWalkerState = LEVEL3;
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PRegEn = 1'b1;
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end
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end
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LEVEL3: begin
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// *** <FUTURE WORK> According to the architecture, we should
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// fault upon finding a superpage that is misaligned or has 0
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// access bit. The following commented line of code is
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// supposed to perform that check. However, it is untested.
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if (ValidPTE && LeafPTE && ~BadTerapage) begin
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NextWalkerState = LEAF;
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TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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end
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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else if (ValidPTE && ~LeafPTE) begin
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NextWalkerState = LEVEL2_SET_ADRE;
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TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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end else begin
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NextWalkerState = FAULT;
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end
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end
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LEVEL2_SET_ADRE: begin
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NextWalkerState = LEVEL2_WDV;
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TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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end
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LEVEL2_WDV: begin
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TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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HPTWRead = 1'b1;
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if (HPTWStall) begin
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NextWalkerState = LEVEL2_WDV;
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end else begin
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NextWalkerState = LEVEL2;
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PRegEn = 1'b1;
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end
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end
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LEVEL2: begin
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// *** <FUTURE WORK> According to the architecture, we should
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// fault upon finding a superpage that is misaligned or has 0
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// access bit. The following commented line of code is
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// supposed to perform that check. However, it is untested.
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if (ValidPTE && LeafPTE && ~BadGigapage) begin
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NextWalkerState = LEAF;
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TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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end
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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else if (ValidPTE && ~LeafPTE) begin
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NextWalkerState = LEVEL1_SET_ADRE;
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TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
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end else begin
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NextWalkerState = FAULT;
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end
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end
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LEVEL1_SET_ADRE: begin
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NextWalkerState = LEVEL1_WDV;
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TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
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end
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LEVEL1_WDV: begin
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TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
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HPTWRead = 1'b1;
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if (HPTWStall) begin
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NextWalkerState = LEVEL1_WDV;
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end else begin
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NextWalkerState = LEVEL1;
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PRegEn = 1'b1;
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end
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end
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LEVEL1: begin
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// *** <FUTURE WORK> According to the architecture, we should
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// fault upon finding a superpage that is misaligned or has 0
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// access bit. The following commented line of code is
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// supposed to perform that check. However, it is untested.
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if (ValidPTE && LeafPTE && ~BadMegapage) begin
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NextWalkerState = LEAF;
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TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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end
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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else if (ValidPTE && ~LeafPTE) begin
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NextWalkerState = LEVEL0_SET_ADRE;
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TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
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end else begin
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NextWalkerState = FAULT;
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end
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end
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LEVEL0_SET_ADRE: begin
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NextWalkerState = LEVEL0_WDV;
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TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
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end
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LEVEL0_WDV: begin
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TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
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HPTWRead = 1'b1;
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if (HPTWStall) begin
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NextWalkerState = LEVEL0_WDV;
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end else begin
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NextWalkerState = LEVEL0;
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PRegEn = 1'b1;
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end
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end
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LEVEL0: begin
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if (ValidPTE && LeafPTE && ~AccessAlert) begin
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NextWalkerState = LEAF;
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TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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end else begin
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NextWalkerState = FAULT;
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end
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end
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LEAF: begin
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PageTableEntry = CurrentPTE;
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PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux?
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((PreviousWalkerState == LEVEL2) ? 2'b10 :
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((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00));
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DTLBWriteM = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
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TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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NextWalkerState = IDLE;
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end
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FAULT: begin
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SelPTW = 1'b0;
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NextWalkerState = IDLE;
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WalkerInstrPageFaultF = ~DTLBMissMQ;
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WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
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WalkerStorePageFaultM = DTLBMissMQ && MemStore;
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end
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// Default case should never happen
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default: begin
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NextWalkerState = IDLE;
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end
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endcase
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end
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// A terapage is a level 3 leaf page. This page must have zero PPN[2],
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// zero PPN[1], and zero PPN[0]
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assign TerapageMisaligned = |(CurrentPPN[26:0]);
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// A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and
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// zero PPN[0]
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assign GigapageMisaligned = |(CurrentPPN[17:0]);
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// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
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assign MegapageMisaligned = |(CurrentPPN[8:0]);
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assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
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assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
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assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
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assign VPN3 = TranslationVAdr[47:39];
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assign VPN2 = TranslationVAdr[38:30];
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assign VPN1 = TranslationVAdr[29:21];
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assign VPN0 = TranslationVAdr[20:12];
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// *** Major issue. We need the full virtual address here.
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// When the TLB's are update it use use the orignal address
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// *** Currently truncate address to 32 bits. This must be changed if
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// we support larger physical address spaces
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assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
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end
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//endgenerate
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end else begin
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assign HPTWPAdrE = 0;
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assign HPTWRead = 0;
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assign WalkerInstrPageFaultF = 0;
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assign WalkerLoadPageFaultM = 0;
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assign WalkerStorePageFaultM = 0;
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|
assign SelPTW = 0;
|
|
end
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endgenerate
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endmodule
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