bbracker bb84354a47 fixed bug where M mode was sensitive to S mode traps		2021-09-07 19:14:39 -04:00
..
csr.sv	Wally previously was overcounting retired instructions when they were flushed.	2021-08-23 12:24:03 -05:00
csrc.sv	Wally previously was overcounting retired instructions when they were flushed.	2021-08-23 12:24:03 -05:00
csri.sv	fixed bug where M mode was sensitive to S mode traps	2021-09-07 19:14:39 -04:00
csrm.sv	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
csrn.sv
csrs.sv	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
csrsr.sv	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
csru.sv	Fixed writting MStatus FS bits	2021-07-13 13:20:30 -04:00
privdec.sv
privileged.sv	Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.	2021-08-23 15:46:17 -05:00
trap.sv	fixed bug where M mode was sensitive to S mode traps	2021-09-07 19:14:39 -04:00