Ross Thompson a7be88a43b Changes to make fpga synthesizable. ... Added preload to test simple program on wally in fpga.		2021-09-22 10:54:13 -05:00
..
cache	Fixed dcache to prevent latches in FPGA synthesized design.	2021-09-11 12:03:48 -05:00
ebu	Additional cleanup of ahblite.	2021-08-25 22:53:20 -05:00
fpu	Changes to make fpga synthesizable.	2021-09-22 10:54:13 -05:00
generic	Changes to make fpga synthesizable.	2021-09-22 10:54:13 -05:00
hazard	Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.	2021-08-23 15:46:17 -05:00
ieu	Moved the ReadDataW register into the datapath.	2021-07-22 14:52:03 -05:00
ifu	Fixed bugs I introduced to the icache.	2021-08-27 15:00:40 -05:00
lsu	Removed amo logic from ahblite. Removed many unused signals from ahblite.	2021-08-25 22:45:13 -05:00
mmu	Lint cleaning, riscv-arch-test testing	2021-09-09 11:05:12 -04:00
muldiv	Restored old integer divider	2021-09-12 22:07:52 -04:00
privileged	fixed bug where M mode was sensitive to S mode traps	2021-09-07 19:14:39 -04:00
uncore	Changes to make fpga synthesizable.	2021-09-22 10:54:13 -05:00
wally	Changes to make fpga synthesizable.	2021-09-22 10:54:13 -05:00