forked from Github_Repos/cvw
275 lines
11 KiB
Systemverilog
275 lines
11 KiB
Systemverilog
///////////////////////////////////////////
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// ifu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Instrunction Fetch Unit
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// PC, branch prediction, instruction cache
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module ifu (
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input logic clk, reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushF, FlushD, FlushE, FlushM, FlushW,
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// Fetch
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input logic [`XLEN-1:0] InstrInF,
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input logic InstrAckF,
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output logic [`XLEN-1:0] PCF,
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output logic [`XLEN-1:0] InstrPAdrF,
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output logic InstrReadF,
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output logic ICacheStallF,
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// Decode
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// Execute
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output logic [`XLEN-1:0] PCLinkE,
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input logic PCSrcE,
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input logic [`XLEN-1:0] PCTargetE,
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output logic [`XLEN-1:0] PCE,
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output logic BPPredWrongE,
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// Mem
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input logic RetM, TrapM,
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input logic [`XLEN-1:0] PrivilegedNextPCM,
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output logic [31:0] InstrD, InstrM,
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output logic [`XLEN-1:0] PCM,
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output logic [4:0] InstrClassM,
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output logic BPPredDirWrongM,
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output logic BTBPredPCWrongM,
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output logic RASPredPCWrongM,
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output logic BPPredClassNonCFIWrongM,
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// Writeback
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// output logic [`XLEN-1:0] PCLinkW,
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// Faults
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input logic IllegalBaseInstrFaultD,
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output logic ITLBInstrPageFaultF,
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output logic IllegalIEUInstrFaultD,
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output logic InstrMisalignedFaultM,
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output logic [`XLEN-1:0] InstrMisalignedAdrM,
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// TLB management
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] PageTableEntryF,
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input logic [1:0] PageTypeF,
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input logic [`XLEN-1:0] SATP_REGW,
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input logic STATUS_MXR, STATUS_SUM,
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input logic ITLBWriteF, ITLBFlushF,
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output logic ITLBMissF, ITLBHitF
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);
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logic [`XLEN-1:0] UnalignedPCNextF, PCNextF;
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logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
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logic PrivilegedChangePCM;
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logic IllegalCompInstrD;
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logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkM, PCNextPF, PCPF;
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logic CompressedF;
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logic [31:0] InstrRawD, InstrE, InstrW;
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localparam [31:0] nop = 32'h00000013; // instruction for NOP
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logic reset_q; // *** look at this later.
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logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
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tlb #(.ENTRY_BITS(3), .ITLB(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF),
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.PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF),
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.TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF),
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.PhysicalAddress(PCPF), .TLBMiss(ITLBMissF),
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.TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF),
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.*);
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// branch predictor signals
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logic SelBPPredF;
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logic [`XLEN-1:0] BPPredPCF, PCCorrectE, PCNext0F, PCNext1F, PCNext2F, PCNext3F;
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logic [4:0] InstrClassD, InstrClassE;
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// *** put memory interface on here, InstrF becomes output
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//assign InstrPAdrF = PCF; // *** no MMU
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//assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
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// assign InstrReadF = 1; // *** & ICacheMissF; add later
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// jarred 2021-03-14 Add instrution cache block to remove rd2
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assign PCNextPF = PCNextF; // Temporary workaround until iTLB is live
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icache icache(
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.*,
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.UpperPCNextPF(PCNextPF[`XLEN-1:12]),
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.LowerPCNextF(PCNextPF[11:0])
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);
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assign PrivilegedChangePCM = RetM | TrapM;
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//mux3 #(`XLEN) pcmux(PCPlus2or4F, PCCorrectE, PrivilegedNextPCM, {PrivilegedChangePCM, BPPredWrongE}, UnalignedPCNextF);
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mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F),
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.d1(BPPredPCF),
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.s(SelBPPredF),
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.y(PCNext0F));
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mux2 #(`XLEN) pcmux1(.d0(PCNext0F),
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.d1(PCCorrectE),
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.s(BPPredWrongE),
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.y(PCNext1F));
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mux2 #(`XLEN) pcmux2(.d0(PCNext1F),
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.d1(PrivilegedNextPCM),
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.s(PrivilegedChangePCM),
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.y(PCNext2F));
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// *** try to remove this in the future as it can add a long path.
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// StallF may arrive late.
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/* -----\/----- EXCLUDED -----\/-----
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mux2 #(`XLEN) pcmux3(.d0(PCNext2F),
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.d1(PCF),
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.s(StallF),
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.y(PCNext3F));
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-----/\----- EXCLUDED -----/\----- */
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mux2 #(`XLEN) pcmux4(.d0(PCNext2F),
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.d1(`RESET_VECTOR),
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.s(reset_q),
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.y(UnalignedPCNextF));
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flop #(1) resetReg (.clk(clk),
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.d(reset),
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.q(reset_q));
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assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
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flopenl #(`XLEN) pcreg(clk, reset, ~StallF & ~ICacheStallF, PCNextF, `RESET_VECTOR, PCF);
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// branch and jump predictor
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generate
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if (`BPRED_ENABLED == 1) begin : bpred
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// I am making the port connection explicit for now as I want to see them and they will be changing.
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bpred bpred(.clk(clk),
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.reset(reset),
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.StallF(StallF),
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.StallD(StallD),
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.StallE(StallE),
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.FlushF(FlushF),
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.FlushD(FlushD),
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.FlushE(FlushE),
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.PCNextF(PCNextF),
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.BPPredPCF(BPPredPCF),
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.SelBPPredF(SelBPPredF),
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.PCE(PCE),
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.PCSrcE(PCSrcE),
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.PCTargetE(PCTargetE),
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.PCD(PCD),
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.PCLinkE(PCLinkE),
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.InstrClassE(InstrClassE),
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.BPPredWrongE(BPPredWrongE),
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.BPPredDirWrongE(BPPredDirWrongE),
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.BTBPredPCWrongE(BTBPredPCWrongE),
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.RASPredPCWrongE(RASPredPCWrongE),
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.BPPredClassNonCFIWrongE(BPPredClassNonCFIWrongE));
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end else begin : bpred
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assign BPPredPCF = {`XLEN{1'b0}};
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assign SelBPPredF = 1'b0;
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assign BPPredWrongE = PCSrcE;
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assign BPPredDirWrongE = 1'b0;
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assign BTBPredPCWrongE = 1'b0;
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assign RASPredPCWrongE = 1'b0;
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assign BPPredClassNonCFIWrong = 1'b0;
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end
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endgenerate
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// The true correct target is PCTargetE if PCSrcE is 1 else it is the fall through PCLinkE.
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assign PCCorrectE = PCSrcE ? PCTargetE : PCLinkE;
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// pcadder
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// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
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assign PCPlusUpperF = PCF[`XLEN-1:2] + 1; // add 4 to PC
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// choose PC+2 or PC+4
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always_comb
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if (CompressedF) // add 2
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if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00};
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else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
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else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
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// Decode stage pipeline register and logic
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flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
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// expand 16-bit compressed instructions to 32 bits
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decompress decomp(.*);
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assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
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// *** combine these with others in better way, including M, F
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// the branch predictor needs a compact decoding of the instruction class.
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// *** consider adding in the alternate return address x5 for returns.
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assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 && (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5
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assign InstrClassD[3] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) == 5'h01; // return must link to ra or r5
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assign InstrClassD[2] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) != 5'h01; // jump register, but not return
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assign InstrClassD[1] = InstrD[6:0] == 7'h6F; // jump
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assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
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// Misaligned PC logic
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generate
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if (`C_SUPPORTED) // C supports compressed instructions on halfword boundaries
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assign misaligned = PCNextF[0];
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else // instructions must be on word boundaries
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assign misaligned = |PCNextF[1:0];
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endgenerate
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// pipeline misaligned faults to M stage
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assign BranchMisalignedFaultE = misaligned & PCSrcE; // E-stage (Branch/Jump) misaligned
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flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, BranchMisalignedFaultM);
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flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM);
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assign TrapMisalignedFaultM = misaligned & PrivilegedChangePCM;
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assign InstrMisalignedFaultM = BranchMisalignedFaultM; // | TrapMisalignedFaultM; *** put this back in without causing a cyclic path
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flopenr #(32) InstrEReg(clk, reset, ~StallE, FlushE ? nop : InstrD, InstrE);
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flopenr #(32) InstrMReg(clk, reset, ~StallM, FlushM ? nop : InstrE, InstrM);
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// flopenr #(32) InstrWReg(clk, reset, ~StallW, FlushW ? nop : InstrM, InstrW); // just for testbench, delete later
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flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
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flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
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// flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later
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flopenrc #(5) InstrClassRegE(.clk(clk),
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.reset(reset),
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.en(~StallE),
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.clear(FlushE),
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.d(InstrClassD),
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.q(InstrClassE));
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flopenrc #(5) InstrClassRegM(.clk(clk),
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.reset(reset),
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.en(~StallM),
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.clear(FlushM),
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.d(InstrClassE),
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.q(InstrClassM));
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flopenrc #(4) BPPredWrongRegM(.clk(clk),
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.reset(reset),
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.en(~StallM),
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.clear(FlushM),
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.d({BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE}),
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.q({BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM}));
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// seems like there should be a lower-cost way of doing this PC+2 or PC+4 for JAL.
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// either have ALU compute PC+2/4 and feed into ALUResult input of ResultMux or
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// have dedicated adder in Mem stage based on PCM + 2 or 4
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// *** redo this
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flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
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flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
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// flopenr #(`XLEN) PCPMReg(clk, reset, ~StallM, PCLinkE, PCLinkM);
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// /flopenr #(`XLEN) PCPWReg(clk, reset, ~StallW, PCLinkM, PCLinkW);
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endmodule
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