Ross Thompson cc48cdc97b Imperas found a real bug in virtual memory. ... If the instruction address spilled across two pages and the second page misses the TLB, the HPTW received a tlb miss at the address of the first page rather than the second. After the walk the TLB was updated with the PTE from the first page at the address of the second page. Example bug Instruction PCF = 0x2ffe First page in 0x2ffe and second page in 0x3000. The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000. TLB is updated with PTE from 0x2ffe at 0x3000.		2023-01-30 11:47:51 -06:00
..
slack-notifier	added instructions to slack notifier	2022-05-18 16:50:31 -07:00
wave-dos	Added generate around uncore.	2022-08-25 10:35:24 -05:00
buildrootBugFinder.py	update to match new filesystem organization	2022-03-26 21:28:32 +00:00
fpga-wave.do	Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.	2022-12-23 15:10:37 -06:00
lint-wally	Clean up unused FPU signals	2022-12-22 23:53:09 -08:00
linux-wave.do	Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.	2022-12-23 15:10:37 -06:00
make-tests.sh	simplified make-tests.sh to run the current makefile in regression	2022-05-17 17:29:34 -07:00
Makefile	Makefile and setup cleanup	2023-01-15 20:27:12 -08:00
makefile-memfile	Clean up warnings from Questa	2023-01-17 13:43:39 -08:00
regression-wally	Removed suggestion about make allclean	2023-01-27 05:57:05 -08:00
sim-buildroot	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
sim-buildroot-batch	sim-buildroot-batch now runs wally-pipelined-batch	2022-07-06 18:06:43 -07:00
sim-testfloat	Running 16-bit square root cases first in testfloat	2022-09-07 11:11:35 -07:00
sim-testfloat-batch	fixed error in divsqrt	2022-07-14 18:16:00 +00:00
sim-wally	FPU test list	2022-12-01 10:18:36 -08:00
sim-wally-batch	Renamed endianswap to match module name	2022-10-04 17:33:49 +00:00
test	test	2023-01-20 15:23:38 -08:00
testfloat.do	Moved fpu modules into subdirectories	2022-09-20 04:12:05 -07:00
wally-harvard.do	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00
wally-pipelined-batch.do	Reverted the IROM/DTIM address range modelsim assignment.	2022-11-30 17:13:33 -06:00
wally-pipelined.do	Updated tests for fpga and BP.	2022-12-18 16:24:26 -06:00
wave-all.do	Changing signal name to ImmExtD/E to match figures	2023-01-17 06:33:58 -08:00
wave-fpu.do	reworked negitive sticky bit handeling in fma	2022-12-23 17:01:34 -06:00
wave.do	Imperas found a real bug in virtual memory.	2023-01-30 11:47:51 -06:00