Ross Thompson a7be88a43b Changes to make fpga synthesizable. ... Added preload to test simple program on wally in fpga.		2021-09-22 10:54:13 -05:00
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clockgater.sv	Changes to make fpga synthesizable.	2021-09-22 10:54:13 -05:00
flop.sv	Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.	2021-07-04 01:19:38 -04:00
lzd.sv	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
mux.sv	Initial (untested) implementation of lr and sc	2021-03-01 00:09:45 -05:00
onehotdecoder.sv	simplified or_rows generation and renamed oneHotDecoder to onehotdecoder	2021-08-25 06:46:41 -04:00
or_rows.sv	Fixed bug with or_rows.	2021-09-11 15:51:11 -05:00
shift.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00