forked from Github_Repos/cvw
f3093ac612
There are a number of combo loops which need fixing outside the icache. They may be fixed in main. We get to instruction address 50 now!
16 lines
843 B
Plaintext
Executable File
16 lines
843 B
Plaintext
Executable File
# check for warnings in Verilog code
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# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
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echo "rv64ic linting..."
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verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv
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echo "rv32ic linting..."
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verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv32ic src/*/*.sv
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#verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv src/*/div/*.sv
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# --lint-only just runs lint rather than trying to compile and simulate
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# -I points to the include directory where files such as `include wally-config.vh are found
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# For more exhaustive (and sometimes spurious) warnings, run:
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# verilator --lint-only -Wall -Iconfig/rv64ic src/*
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# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.
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