forked from Github_Repos/cvw
117 lines
4.7 KiB
Systemverilog
117 lines
4.7 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtfsm.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtfsm(
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input logic clk,
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input logic reset,
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input logic [`DIVb+3:0] NextWSN, NextWCN, WS, WC,
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input logic XInfE, YInfE,
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input logic XZeroE, YZeroE,
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input logic XNaNE, YNaNE,
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input logic DivStart,
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input logic XsE,
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input logic SqrtE,
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input logic SqrtM,
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input logic StallE,
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input logic StallM,
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input logic [`DIVN-2:0] D, // U0.N-1
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input logic [`DIVb+3:0] StickyWSA,
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input logic [`DURLEN-1:0] Dur,
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input logic [`DIVb:0] LastSM,
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input logic [`DIVb:0] FirstSM,
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input logic [`DIVb-1:0] LastC,
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input logic [`DIVb-1:0] FirstC,
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input logic [`DIVCOPIES-1:0] qn,
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output logic [`DURLEN-1:0] EarlyTermShiftE,
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output logic DivSE,
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output logic DivDone,
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output logic NegSticky,
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output logic DivBusy
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);
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typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
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statetype state;
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logic [`DURLEN-1:0] step;
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logic WZero;
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//logic [$clog2(`DIVLEN/2+3)-1:0] Dur;
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logic [`DIVb+3:0] W;
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logic SpecialCase;
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logic WZeroDelayed; // *** later remove
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//flopen #($clog2(`DIVLEN/2+3)) durflop(clk, DivStart, CalcDur, Dur);
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assign DivBusy = (state == BUSY);
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// calculate sticky bit
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// - there is a chance that a value is subtracted infinitly, resulting in an exact QM result
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// this is only a problem on radix 2 (and possibly maximally redundant 4) since minimally redundant
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// radix-4 division can't create a QM that continually adds 0's
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if (`RADIX == 2) begin
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logic [`DIVb+3:0] FZero, FSticky;
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logic [`DIVb+2:0] LastK, FirstK;
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assign LastK = ({3'b111, LastC} & ~({3'b111, LastC} << 1));
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assign FirstK = ({3'b111, FirstC<<1} & ~({3'b111, FirstC<<1} << 1));
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assign FZero = SqrtM ? {LastSM[`DIVb], LastSM, 2'b0} | {LastK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
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assign FSticky = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
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// *** |... for continual -1 is not efficent fix - also only needed for radix-2
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assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVb+2:0]|NextWCN[`DIVb+2:0], 1'b0})|(((NextWSN+NextWCN+FZero)==0)&qn[`DIVCOPIES-1]);
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assign DivSE = |W&~((W+FSticky)==0); //***not efficent fix == and need the & qn
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end else begin
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assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVb+2:0]|NextWCN[`DIVb+2:0], 1'b0});
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assign DivSE = |W;
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end
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flopr #(1) WZeroReg(clk, reset | DivStart, WZero, WZeroDelayed);
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assign DivDone = (state == DONE) | WZeroDelayed;
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assign W = WC+WS;
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assign NegSticky = W[`DIVb+3];
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assign EarlyTermShiftE = step;
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// terminate immediately on special cases
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assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
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always_ff @(posedge clk) begin
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if (reset) begin
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state <= #1 IDLE;
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end else if (DivStart&~StallE) begin
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step <= Dur;
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if (SpecialCase) state <= #1 DONE;
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else state <= #1 BUSY;
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end else if (DivDone) begin
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if (StallM) state <= #1 DONE;
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else state <= #1 IDLE;
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end else if (state == BUSY) begin
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if (step == 0) begin
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state <= #1 DONE;
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end
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step <= step - 1;
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end
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end
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endmodule |