forked from Github_Repos/cvw
239 lines
10 KiB
Systemverilog
239 lines
10 KiB
Systemverilog
///////////////////////////////////////////
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// testbench-imperas.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Wally Testbench and helper modules
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// Applies test programs from the Imperas suite
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module testbench();
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logic clk;
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logic reset;
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int test, i, errors, totalerrors;
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logic [31:0] sig32[10000:0];
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logic [`XLEN-1:0] signature[10000:0];
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logic [`XLEN-1:0] testadr;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [`XLEN-1:0] meminit;
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string tests[];
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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// pick tests based on modes supported
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initial
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tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremarkcodemod.bare.riscv.memfile", "1000"};
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string signame, memfilename;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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// instantiate device to be tested
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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assign HREADYEXT = 1;
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assign HRESPEXT = 0;
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assign HRDATAEXT = 0;
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wallypipelinedsoc dut(.*);
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logic [31:0] InstrW;
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flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
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// Track names of instructions
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.icache.controller.FinalInstrRawF,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, InstrW,
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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logic [`XLEN-1:0] PCW;
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flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW);
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// initialize tests
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integer j;
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initial
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begin
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totalerrors = 0;
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// read test vectors into memory
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memfilename = tests[0];
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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//for(j=268437955; j < 268566528; j = j+1)
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//dut.uncore.dtim.RAM[j] = 64'b0;
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// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";
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// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab";
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//dut.uncore.dtim.RAM[268437713]=64'b1;
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reset = 1; # 22; reset = 0;
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end
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// generate clock to sequence tests
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always
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begin
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clk = 1; # 5; clk = 0; # 5;
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end
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always @(negedge clk)
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begin
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if (dut.hart.priv.ecallM) begin
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#20;
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$display("Code ended with ebreakM");
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$stop;
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end
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end
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initial begin
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$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
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$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
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end
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endmodule
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/* verilator lint_on STMTDLY */
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/* verilator lint_on WIDTH */
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module instrTrackerTB(
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input logic clk, reset, FlushE,
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input logic [31:0] InstrF, InstrD,
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input logic [31:0] InstrE, InstrM,
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input logic [31:0] InstrW,
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output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// stage Instr to Writeback for visualization
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instrNameDecTB fdec(InstrF, InstrFName);
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instrNameDecTB ddec(InstrD, InstrDName);
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instrNameDecTB edec(InstrE, InstrEName);
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instrNameDecTB mdec(InstrM, InstrMName);
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instrNameDecTB wdec(InstrW, InstrWName);
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endmodule
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// decode the instruction name, to help the test bench
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module instrNameDecTB(
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input logic [31:0] instr,
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output string name);
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logic [6:0] op;
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logic [2:0] funct3;
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logic [6:0] funct7;
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logic [11:0] imm;
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assign op = instr[6:0];
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assign funct3 = instr[14:12];
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assign funct7 = instr[31:25];
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assign imm = instr[31:20];
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// it would be nice to add the operands to the name
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// create another variable called decoded
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always_comb
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casez({op, funct3})
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10'b0000000_000: name = "BAD";
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10'b0000011_000: name = "LB";
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10'b0000011_001: name = "LH";
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10'b0000011_010: name = "LW";
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10'b0000011_011: name = "LD";
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10'b0000011_100: name = "LBU";
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10'b0000011_101: name = "LHU";
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10'b0000011_110: name = "LWU";
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10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
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else name = "ADDI";
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10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
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else name = "ILLEGAL";
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10'b0010011_010: name = "SLTI";
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10'b0010011_011: name = "SLTIU";
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10'b0010011_100: name = "XORI";
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10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
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else if (funct7[6:1] == 6'b010000) name = "SRAI";
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else name = "ILLEGAL";
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10'b0010011_110: name = "ORI";
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10'b0010011_111: name = "ANDI";
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10'b0010111_???: name = "AUIPC";
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10'b0100011_000: name = "SB";
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10'b0100011_001: name = "SH";
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10'b0100011_010: name = "SW";
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10'b0100011_011: name = "SD";
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10'b0011011_000: name = "ADDIW";
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10'b0011011_001: name = "SLLIW";
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10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
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else if (funct7 == 7'b0100000) name = "SRAIW";
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else name = "ILLEGAL";
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10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
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else if (funct7 == 7'b0100000) name = "SUBW";
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else if (funct7 == 7'b0000001) name = "MULW";
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else name = "ILLEGAL";
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10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW";
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else if (funct7 == 7'b0000001) name = "DIVW";
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else name = "ILLEGAL";
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10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
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else if (funct7 == 7'b0100000) name = "SRAW";
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else if (funct7 == 7'b0000001) name = "DIVUW";
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else name = "ILLEGAL";
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10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW";
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else name = "ILLEGAL";
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10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW";
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else name = "ILLEGAL";
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10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
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else if (funct7 == 7'b0000001) name = "MUL";
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else if (funct7 == 7'b0100000) name = "SUB";
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else name = "ILLEGAL";
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10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
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else if (funct7 == 7'b0000001) name = "MULH";
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else name = "ILLEGAL";
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10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
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else if (funct7 == 7'b0000001) name = "MULHSU";
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else name = "ILLEGAL";
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10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
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else if (funct7 == 7'b0000001) name = "MULHU";
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else name = "ILLEGAL";
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10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
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else if (funct7 == 7'b0000001) name = "DIV";
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else name = "ILLEGAL";
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10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
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else if (funct7 == 7'b0000001) name = "DIVU";
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else if (funct7 == 7'b0100000) name = "SRA";
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else name = "ILLEGAL";
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10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
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else if (funct7 == 7'b0000001) name = "REM";
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else name = "ILLEGAL";
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10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
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else if (funct7 == 7'b0000001) name = "REMU";
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else name = "ILLEGAL";
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10'b0110111_???: name = "LUI";
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10'b1100011_000: name = "BEQ";
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10'b1100011_001: name = "BNE";
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10'b1100011_100: name = "BLT";
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10'b1100011_101: name = "BGE";
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10'b1100011_110: name = "BLTU";
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10'b1100011_111: name = "BGEU";
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10'b1100111_000: name = "JALR";
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10'b1101111_???: name = "JAL";
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10'b1110011_000: if (imm == 0) name = "ECALL";
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else if (imm == 1) name = "EBREAK";
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else if (imm == 2) name = "URET";
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else if (imm == 258) name = "SRET";
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else if (imm == 770) name = "MRET";
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else name = "ILLEGAL";
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10'b1110011_001: name = "CSRRW";
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10'b1110011_010: name = "CSRRS";
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10'b1110011_011: name = "CSRRC";
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10'b1110011_101: name = "CSRRWI";
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10'b1110011_110: name = "CSRRSI";
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10'b1110011_111: name = "CSRRCI";
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10'b0001111_???: name = "FENCE";
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default: name = "ILLEGAL";
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endcase
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endmodule
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