Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
6b3d056713
cvw/synthDC
History
David Harris 6b3d056713 ../synthDC/Makefile
2023-02-04 04:19:09 -08:00
..
ppa explanations and modifications for general ppa use 2022-07-09 03:24:47 +00:00
scripts Fixed merge issues on synthDC PR 2023-02-04 04:13:40 -08:00
.synopsys_dc.setup Fixed typo in DC setup for memories 2023-02-01 05:49:30 -08:00
extractSummary.py Fixed config file writing for synthesis (#29) 2023-01-26 06:58:15 +02:00
Makefile ../synthDC/Makefile 2023-02-04 04:19:09 -08:00
README.md Slight tweaks to synthDC for library variables 2022-02-10 17:56:27 -06:00
wallySynth.py finishing the job of the last commit 2023-02-04 10:24:01 +00:00

README.md

Synthesis for RISC-V Microprocessor System-on-Chip Design

This subdirectory contains synthesis scripts for use with Synopsys (snps) Design Compiler (DC). Synthesis commands are found in scripts/synth.tcl.

Example Usage make synth DESIGN=wallypipelinedcore FREQ=500

environment variables

DESIGN Design provides the name of the output log. Default is synth.

FREQ Frequency in MHz. Default is 500

CONFIG The Wally configuration file. The default is rv32e. Examples: rv32e, rv64gc, rv32gc

TECH The target standard cell library. The default is sky130. sky90: skywater 90nm TT 25C sky130: skywater 130nm TT 25C

SAIFPOWER Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif. The default is 0. 0: switching factor power analysis 1: RTL simulation driven power analysis.