forked from Github_Repos/cvw
136 lines
3.1 KiB
ArmAsm
136 lines
3.1 KiB
ArmAsm
// -----------
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// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
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// version : 0.5.1
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// timestamp : Wed Aug 4 06:39:00 2021 GMT
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// usage : riscv_ctg \
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// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
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// --base-isa rv32e \
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// --randomize
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// -----------
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//
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// -----------
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// Copyright (c) 2020. RISC-V International. All rights reserved.
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the c.lw instruction of the RISC-V C extension for the clw covergroup.
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//
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV32EC")
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clw)
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RVTEST_SIGBASE( x1,signature_x1_1)
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inst_0:
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// rs1 == rd, rd==x8, rs1==x8, imm_val == 0,
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// opcode: c.lw; op1:x8; dest:x8; immval:0x0
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TEST_LOAD(x1,x2,0,x8,x8,0x0,0,c.lw,0)
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inst_1:
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// rs1 != rd, rd==x14, rs1==x12, imm_val == 60, imm_val > 0
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// opcode: c.lw; op1:x12; dest:x14; immval:0x3c
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TEST_LOAD(x1,x2,0,x12,x14,0x3c,4,c.lw,0)
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inst_2:
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// rd==x15, rs1==x11, imm_val == 92,
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// opcode: c.lw; op1:x11; dest:x15; immval:0x5c
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TEST_LOAD(x1,x2,0,x11,x15,0x5c,8,c.lw,0)
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inst_3:
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// rd==x10, rs1==x15, imm_val == 108,
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// opcode: c.lw; op1:x15; dest:x10; immval:0x6c
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TEST_LOAD(x1,x2,0,x15,x10,0x6c,12,c.lw,0)
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inst_4:
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// rd==x13, rs1==x14, imm_val == 116,
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// opcode: c.lw; op1:x14; dest:x13; immval:0x74
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TEST_LOAD(x1,x2,0,x14,x13,0x74,16,c.lw,0)
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inst_5:
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// rd==x11, rs1==x13, imm_val == 120,
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// opcode: c.lw; op1:x13; dest:x11; immval:0x78
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TEST_LOAD(x1,x2,0,x13,x11,0x78,20,c.lw,0)
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inst_6:
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// rd==x12, rs1==x10, imm_val == 64,
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// opcode: c.lw; op1:x10; dest:x12; immval:0x40
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TEST_LOAD(x1,x2,0,x10,x12,0x40,24,c.lw,0)
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inst_7:
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// rd==x9, imm_val == 32,
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// opcode: c.lw; op1:x10; dest:x9; immval:0x20
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TEST_LOAD(x1,x2,0,x10,x9,0x20,28,c.lw,0)
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inst_8:
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// rs1==x9, imm_val == 16,
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// opcode: c.lw; op1:x9; dest:x8; immval:0x10
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TEST_LOAD(x1,x2,0,x9,x8,0x10,32,c.lw,0)
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inst_9:
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// imm_val == 8,
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// opcode: c.lw; op1:x11; dest:x10; immval:0x8
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TEST_LOAD(x1,x2,0,x11,x10,0x8,36,c.lw,0)
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inst_10:
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// imm_val == 4,
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// opcode: c.lw; op1:x11; dest:x10; immval:0x4
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TEST_LOAD(x1,x2,0,x11,x10,0x4,40,c.lw,0)
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inst_11:
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// imm_val == 40,
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// opcode: c.lw; op1:x11; dest:x10; immval:0x28
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TEST_LOAD(x1,x2,0,x11,x10,0x28,44,c.lw,0)
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inst_12:
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// imm_val == 84,
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// opcode: c.lw; op1:x11; dest:x10; immval:0x54
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TEST_LOAD(x1,x2,0,x11,x10,0x54,48,c.lw,0)
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#endif
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RVTEST_CODE_END
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RVMODEL_HALT
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RVTEST_DATA_BEGIN
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.align 4
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rvtest_data:
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.word 0xbabecafe
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RVTEST_DATA_END
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RVMODEL_DATA_BEGIN
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signature_x1_0:
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.fill 0*(XLEN/32),4,0xdeadbeef
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signature_x1_1:
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.fill 13*(XLEN/32),4,0xdeadbeef
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#ifdef rvtest_mtrap_routine
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mtrap_sigptr:
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.fill 64*(XLEN/32),4,0xdeadbeef
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#endif
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#ifdef rvtest_gpr_save
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gpr_save:
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.fill 32*(XLEN/32),4,0xdeadbeef
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#endif
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RVMODEL_DATA_END
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