// ----------- // This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg) // version : 0.5.1 // timestamp : Wed Aug 4 06:39:00 2021 GMT // usage : riscv_ctg \ // --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \ // --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \ // --base-isa rv32e \ // --randomize // ----------- // // ----------- // Copyright (c) 2020. RISC-V International. All rights reserved. // SPDX-License-Identifier: BSD-3-Clause // ----------- // // This assembly file tests the c.lw instruction of the RISC-V C extension for the clw covergroup. // #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32EC") .section .text.init .globl rvtest_entry_point rvtest_entry_point: RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clw) RVTEST_SIGBASE( x1,signature_x1_1) inst_0: // rs1 == rd, rd==x8, rs1==x8, imm_val == 0, // opcode: c.lw; op1:x8; dest:x8; immval:0x0 TEST_LOAD(x1,x2,0,x8,x8,0x0,0,c.lw,0) inst_1: // rs1 != rd, rd==x14, rs1==x12, imm_val == 60, imm_val > 0 // opcode: c.lw; op1:x12; dest:x14; immval:0x3c TEST_LOAD(x1,x2,0,x12,x14,0x3c,4,c.lw,0) inst_2: // rd==x15, rs1==x11, imm_val == 92, // opcode: c.lw; op1:x11; dest:x15; immval:0x5c TEST_LOAD(x1,x2,0,x11,x15,0x5c,8,c.lw,0) inst_3: // rd==x10, rs1==x15, imm_val == 108, // opcode: c.lw; op1:x15; dest:x10; immval:0x6c TEST_LOAD(x1,x2,0,x15,x10,0x6c,12,c.lw,0) inst_4: // rd==x13, rs1==x14, imm_val == 116, // opcode: c.lw; op1:x14; dest:x13; immval:0x74 TEST_LOAD(x1,x2,0,x14,x13,0x74,16,c.lw,0) inst_5: // rd==x11, rs1==x13, imm_val == 120, // opcode: c.lw; op1:x13; dest:x11; immval:0x78 TEST_LOAD(x1,x2,0,x13,x11,0x78,20,c.lw,0) inst_6: // rd==x12, rs1==x10, imm_val == 64, // opcode: c.lw; op1:x10; dest:x12; immval:0x40 TEST_LOAD(x1,x2,0,x10,x12,0x40,24,c.lw,0) inst_7: // rd==x9, imm_val == 32, // opcode: c.lw; op1:x10; dest:x9; immval:0x20 TEST_LOAD(x1,x2,0,x10,x9,0x20,28,c.lw,0) inst_8: // rs1==x9, imm_val == 16, // opcode: c.lw; op1:x9; dest:x8; immval:0x10 TEST_LOAD(x1,x2,0,x9,x8,0x10,32,c.lw,0) inst_9: // imm_val == 8, // opcode: c.lw; op1:x11; dest:x10; immval:0x8 TEST_LOAD(x1,x2,0,x11,x10,0x8,36,c.lw,0) inst_10: // imm_val == 4, // opcode: c.lw; op1:x11; dest:x10; immval:0x4 TEST_LOAD(x1,x2,0,x11,x10,0x4,40,c.lw,0) inst_11: // imm_val == 40, // opcode: c.lw; op1:x11; dest:x10; immval:0x28 TEST_LOAD(x1,x2,0,x11,x10,0x28,44,c.lw,0) inst_12: // imm_val == 84, // opcode: c.lw; op1:x11; dest:x10; immval:0x54 TEST_LOAD(x1,x2,0,x11,x10,0x54,48,c.lw,0) #endif RVTEST_CODE_END RVMODEL_HALT RVTEST_DATA_BEGIN .align 4 rvtest_data: .word 0xbabecafe RVTEST_DATA_END RVMODEL_DATA_BEGIN signature_x1_0: .fill 0*(XLEN/32),4,0xdeadbeef signature_x1_1: .fill 13*(XLEN/32),4,0xdeadbeef #ifdef rvtest_mtrap_routine mtrap_sigptr: .fill 64*(XLEN/32),4,0xdeadbeef #endif #ifdef rvtest_gpr_save gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif RVMODEL_DATA_END