cvw/pipelined/src/lsu
2022-04-12 17:56:23 -05:00
..
atomic.sv atomic cleanup. 2022-03-10 18:56:37 -06:00
busdp.sv Marked signals for name changes. 2022-03-08 17:41:02 -06:00
busfsm.sv Found the complex TrapM giving back the wrong instruction bug. 2022-04-11 13:07:52 -05:00
dtim.sv Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload. 2022-03-30 11:04:15 -05:00
interlockfsm.sv atomic cleanup. 2022-03-10 18:56:37 -06:00
lrsc.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
lsu.sv Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
lsuvirtmen.sv Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB. 2022-03-24 23:47:28 -05:00
subwordread.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
subwordwrite.sv Name changes. 2022-03-10 18:50:03 -06:00
swbytemask.sv fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00