Ross Thompson c3b43b2fac Waiting on fix for wally64periph uart test. ... would like to remove vectored interrupt adder.		2022-12-21 13:16:09 -06:00
..
csr.sv	Waiting on fix for wally64periph uart test.	2022-12-21 13:16:09 -06:00
csrc.sv	Clean up unused signals	2022-05-12 14:49:58 +00:00
csri.sv	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
csrm.sv	Fixed typo in csrm	2022-05-12 06:55:39 -07:00
csrs.sv	Updated fpga debugger.	2022-05-17 23:04:01 -05:00
csrsr.sv	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
csru.sv	Illegal instruction fault when running FPU instruction with STATUS_FS = 0	2022-05-03 18:32:01 +00:00
privdec.sv	Replaced || and && with single ops	2022-12-20 01:33:35 -08:00
privileged.sv	Moved privileged pc logic into privileged unit.	2022-12-20 17:55:45 -06:00
privmode.sv	../src/privileged/csrc.sv	2022-05-31 21:12:17 +00:00
privpiperegs.sv	Cleaned up fcvt selection control to IEU and FPUIllegalInst signals	2022-08-23 12:17:19 -07:00
trap.sv	Replaced || and && with single ops	2022-12-20 01:33:35 -08:00