cvw/wally-pipelined
Ross Thompson 551e3491af Moved the ReadDataW register into the datapath.
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
..
bin Icache integrated! 2021-04-26 11:48:58 -05:00
config fix UART RX FIFO bug where tail pointer can overtake head pointer 2021-07-22 02:09:41 -04:00
linux-testgen fix UART RX FIFO bug where tail pointer can overtake head pointer 2021-07-22 02:09:41 -04:00
misc Clean up MMU code 2021-05-14 07:12:32 -04:00
ppa Config file for ppa experiments 2021-03-25 10:23:21 -05:00
regression Moved the ReadDataW register into the datapath. 2021-07-22 14:52:03 -05:00
src Moved the ReadDataW register into the datapath. 2021-07-22 14:52:03 -05:00
testbench Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken. 2021-07-22 14:18:27 -04:00
testgen mcause test fixes and s-mode interrupt bugfix 2021-06-16 17:37:08 -04:00
lint-wally Merge difficulties 2021-06-07 09:50:23 -04:00