cvw/pipelined/src
2022-09-07 10:54:27 -05:00
..
cache Moved files around. 2022-08-31 14:08:06 -05:00
ebu Added logic to make burst optional. 2022-09-06 09:21:21 -05:00
fpu Continued simplifying fdivsqrt postprocessing 2022-09-07 07:02:22 -07:00
generic James found a bug in synchronizer. Was not actually back to back flip flops. 2022-09-06 15:06:54 -05:00
hazard Added comments about planned changes. 2022-08-29 09:48:00 -05:00
ieu Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
ifu marked possible improvement to ahb bus fsms. 2022-08-31 23:57:08 -05:00
lsu Possible fix to AHB burst eviction bug. If HREADY went low during a burst seq the next data phase would only last 1 cycle. 2022-09-02 19:58:41 -05:00
mmu Created two new pma regions for dtim and irom. 2022-08-28 13:50:50 -05:00
muldiv Clean up unused signals 2022-05-12 14:49:58 +00:00
ppa cleanup, plots for paper 2022-06-15 18:28:36 +00:00
privileged Cleaned up fcvt selection control to IEU and FPUIllegalInst signals 2022-08-23 12:17:19 -07:00
uncore Added generate around the longer latency version of the ram_ahb.sv 2022-09-06 09:21:03 -05:00
wally Removed old signals. 2022-08-31 09:50:39 -05:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00