bbracker 005f838b8d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main		2021-04-08 14:28:25 -04:00
..
wave-dos	merge testbench	2021-04-08 14:28:01 -04:00
regression-wally.py	regression: use busybear batch instead	2021-03-25 15:34:10 -04:00
run_sim.sh	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
sim-busybear	busybear: add sim-busybear and sim-busybear-batch based on sim-wally	2021-03-01 21:01:15 +00:00
sim-busybear-batch	busybear: make a second .do file with better optimization for command line mode	2021-03-08 19:35:00 +00:00
sim-peripherals	Yee hoo first draft of PLIC plus self-checking tests	2021-04-04 06:40:53 -04:00
sim-wally	Added test configurations	2021-01-25 11:28:43 -05:00
sim-wally-batch	Fixed issue with sim-wally-batch. Are people still using this script?	2021-03-17 11:17:52 -05:00
sim-wally-batch-muldiv	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
sim-wally-batch-rv32ic	fixed sim-wally-32ic	2021-04-08 13:40:16 -04:00
sim-wally-rv32ic	fixed sim-wally-32ic	2021-04-08 13:40:16 -04:00
vish_stacktrace.vstf	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
wally-busybear-batch.do	busybear: clean up questa warnings	2021-03-31 14:02:15 -04:00
wally-busybear.do	busybear: clean up questa warnings	2021-03-31 14:02:15 -04:00
wally-coremark_bare.do	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
wally-coremark.do	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
wally-pipelined-batch-muldiv.do	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
wally-pipelined-batch.do	Condense the parallel and non-parallel wally-pipelined-batch.do files into one	2021-03-16 18:15:13 -04:00
wally-pipelined-muldiv.do	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
wally-pipelined-ross.do	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
wally-pipelined.do	merge testbench	2021-04-08 14:28:01 -04:00
wally-privileged.do	Fix bugs with privileged tests	2021-03-25 14:06:05 -04:00
wave-all.do	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
wave.do	Partial fix to the integer divide stall issue.	2021-04-02 15:32:15 -05:00