Ross Thompson 7fe70c3cc6 Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages. ... 1: It simplifies the interactions between the caches and the hptw. 2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process. There are two downsides. 1: Pollute the TLBs with not very relavent translations 2: Have to compute the misalignment. This can be cached in the TLB which only costs 1 flip flop for each TLB line.		2021-12-23 12:40:22 -06:00
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cache	It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.	2021-12-21 15:59:56 -06:00
ebu	Added more debugging code for FPGA.	2021-12-17 14:40:25 -06:00
fpu	Moved generate statements for optional units into wallypipelinedhart	2021-12-19 16:53:41 -08:00
generic	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
hazard	Added proper credit to Richard Davis, the author of the original sd card reader.	2021-12-12 15:05:50 -06:00
ieu	ALUControl cleanup	2021-12-19 13:53:45 -08:00
ifu	Fixed complex bug where FENCE is instruction class miss predicted as a taken branch.	2021-12-21 11:29:28 -06:00
lsu	It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.	2021-12-21 15:59:56 -06:00
mmu	Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages.	2021-12-23 12:40:22 -06:00
muldiv	Moved generate statements for optional units into wallypipelinedhart	2021-12-19 16:53:41 -08:00
privileged	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-12-20 21:09:20 -08:00
sdc	Moved generate statements for optional units into wallypipelinedhart	2021-12-19 16:53:41 -08:00
uncore	Oups missed files in the last commit.	2021-12-15 10:25:08 -06:00
wally	Moved generate of conditional units to hart	2021-12-19 17:03:57 -08:00