forked from Github_Repos/cvw
509a0cd3f8
only at the start of a request. Pending interrupt was used to start one of these suppressions; however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an interrupt becam pending then the the next request (eviction) made by the cache was also suppressed. This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request to the bus fsm, but the pending interrupt ignored the request. The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
118 lines
5.6 KiB
Systemverilog
118 lines
5.6 KiB
Systemverilog
///////////////////////////////////////////
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// interlockfsm.sv
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//
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// Written: Ross Thompson ross1728@gmail.com December 29, 2021
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// Modified:
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//
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// Purpose: Allows the HPTW to take control of the dcache to walk page table and then replay the memory operation if
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// there was on.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module interlockfsm
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(input logic clk,
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input logic reset,
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input logic AnyCPUReqM,
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input logic ITLBMissF,
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input logic ITLBWriteF,
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input logic DTLBMissM,
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input logic DTLBWriteM,
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input logic TrapM,
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input logic DCacheStall,
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output logic InterlockStall,
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output logic SelReplayCPURequest,
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output logic SelHPTW,
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output logic IgnoreRequest);
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typedef enum {STATE_T0_READY,
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STATE_T0_REPLAY,
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STATE_T3_DTLB_MISS,
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STATE_T4_ITLB_MISS,
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STATE_T5_ITLB_MISS,
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STATE_T7_DITLB_MISS} statetype;
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statetype InterlockCurrState, InterlockNextState;
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always_ff @(posedge clk)
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if (reset) InterlockCurrState <= #1 STATE_T0_READY;
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else InterlockCurrState <= #1 InterlockNextState;
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always_comb begin
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case(InterlockCurrState)
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STATE_T0_READY: if(~ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS;
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else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) InterlockNextState = STATE_T4_ITLB_MISS;
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else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T5_ITLB_MISS;
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else if(ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T7_DITLB_MISS;
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else InterlockNextState = STATE_T0_READY;
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STATE_T0_REPLAY: if(DCacheStall) InterlockNextState = STATE_T0_REPLAY;
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else InterlockNextState = STATE_T0_READY;
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STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY;
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else InterlockNextState = STATE_T3_DTLB_MISS;
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STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY;
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else InterlockNextState = STATE_T4_ITLB_MISS;
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STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY;
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else InterlockNextState = STATE_T5_ITLB_MISS;
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STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS;
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else InterlockNextState = STATE_T7_DITLB_MISS;
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default: InterlockNextState = STATE_T0_READY;
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endcase
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end // always_comb
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// signal to CPU it needs to wait on HPTW.
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/* -----\/----- EXCLUDED -----\/-----
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// this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates
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// everywhere. The case statement below implements the same logic but any x on the inputs will resolve to 0.
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// Note this will cause a problem for post synthesis gate simulation.
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assign InterlockStall = (InterlockCurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) |
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(InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
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(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
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-----/\----- EXCLUDED -----/\----- */
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always_comb begin
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InterlockStall = 1'b0;
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case(InterlockCurrState)
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STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1;
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STATE_T3_DTLB_MISS: InterlockStall = 1'b1;
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STATE_T4_ITLB_MISS: InterlockStall = 1'b1;
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STATE_T5_ITLB_MISS: InterlockStall = 1'b1;
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STATE_T7_DITLB_MISS: InterlockStall = 1'b1;
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default: InterlockStall = 1'b0;
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endcase
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end
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assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY);
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assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
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(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
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assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | TrapM)) |
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((InterlockCurrState == STATE_T0_REPLAY)
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& (TrapM));
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endmodule
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