forked from Github_Repos/cvw
55 lines
2.3 KiB
Systemverilog
55 lines
2.3 KiB
Systemverilog
///////////////////////////////////////////
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// dtim.sv
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//
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// Written: Ross Thompson ross1728@gmail.com January 30, 2022
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// Modified:
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//
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// Purpose: simple memory with bus or cache.
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module dtim(
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input logic clk, reset,
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input logic [1:0] LSURWM,
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input logic [`XLEN-1:0] IEUAdrE,
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input logic TrapM,
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input logic [`LLEN-1:0] WriteDataM,
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input logic [`LLEN/8-1:0] ByteMaskM,
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input logic Cacheable,
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output logic [`LLEN-1:0] ReadDataWordM
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);
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logic we;
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// localparam ADDR_WDITH = $clog2(`TIM_RAM_RANGE/8); // *** replace with tihs when defined
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localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size
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localparam OFFSET = $clog2(`LLEN/8);
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assign we = LSURWM[0] & Cacheable & ~TrapM; // have to ignore write if Trap.
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bram1p1rw #(`LLEN/8, 8, ADDR_WDITH)
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ram(.clk, .we, .bwe(ByteMaskM), .addr(IEUAdrE[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
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endmodule
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