Alec Vercruysse 3de03abd9d add D$ test case to trigger a FlushStage while SetDirtyWay=1 ... This hits some conditional coverage in each cacheway. A cache store hit happens at the same time as a StoreAmoMisalignedFault.		2023-04-19 01:34:01 -07:00
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coverage	add D$ test case to trigger a FlushStage while SetDirtyWay=1	2023-04-19 01:34:01 -07:00
custom	*.out removal	2023-04-05 12:50:26 -07:00
fp	integrated tv generation for IFdivsqrt	2023-03-29 20:57:26 -07:00
riscof	Removed unused ISA string from spike YAML	2023-03-22 13:23:52 -07:00
testgen	Added RVTEST_CASE to testgen header	2023-02-09 18:25:24 -08:00
wally-riscv-arch-test	restored original virt mem tests when svadu is not supported	2023-04-11 18:47:08 -07:00