|
|
||
|---|---|---|
| .. | ||
| nm_500_MHz_2022-03-22-20-43_2947df5b | ||
| scripts | ||
| .synopsys_dc.setup | ||
| crte_000012580.txt | ||
| crte_000032764.txt | ||
| crte_000052064.txt | ||
| crte_000055441.txt | ||
| crte_000057184.txt | ||
| crte_000057185.txt | ||
| extractSummary.py | ||
| Makefile | ||
| ppa | ||
| ppaAnalyze.py | ||
| ppaData.csv | ||
| ppaFitting.csv | ||
| ppaSynth.py | ||
| README.md | ||
| runConfigsSynth.sh | ||
| runFrequencySynth.sh | ||
| Synopsys_stack_trace_12580.txt | ||
| Synopsys_stack_trace_32764.txt | ||
| Synopsys_stack_trace_52064.txt | ||
| Synopsys_stack_trace_55441.txt | ||
| Synopsys_stack_trace_57184.txt | ||
| Synopsys_stack_trace_57185.txt | ||
Synthesis for RISC-V Microprocessor System-on-Chip Design
This subdirectory contains synthesis scripts for use with Synopsys (snps) Design Compiler (DC). Synthesis commands are found in scripts/synth.tcl.
Example Usage make synth DESIGN=wallypipelinedcore FREQ=500
environment variables
DESIGN Design provides the name of the output log. Default is synth.
FREQ Frequency in MHz. Default is 500
CONFIG The Wally configuration file. The default is rv32e. Examples: rv32e, rv64gc, rv32gc
TECH The target standard cell library. The default is sky130. sky90: skywater 90nm TT 25C sky130: skywater 130nm TT 25C
SAIFPOWER Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif. The default is 0. 0: switching factor power analysis 1: RTL simulation driven power analysis.