Ross Thompson a64a37d702 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.		2021-03-30 23:18:20 -05:00
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BTBPredictor.txt	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
twoBitPredictor.txt	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
wally-config.vh	Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.	2021-03-30 23:18:20 -05:00
wally-constants.vh	Place tlb parameters into constant header file	2021-03-05 13:35:24 -05:00