Ross Thompson
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a64a37d702
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Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
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2021-03-30 23:18:20 -05:00 |
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bbracker
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11d4a8ab34
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first pass at PLIC interface
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2021-03-22 10:14:21 -04:00 |
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Shreya Sanghai
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bbe0957df5
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Merge branch 'gshare' into main
Conflicts:
wally-pipelined/regression/wave.do
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2021-03-18 17:25:48 -04:00 |
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Ross Thompson
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1091dd10c1
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Switched to gshare from global history.
Fixed a few minor bugs.
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2021-03-18 16:05:59 -05:00 |
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Noah Boorstin
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bc1a0c6ee7
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change ifndef to generate/if
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2021-03-18 12:50:19 -04:00 |
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Noah Boorstin
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a2b0af460e
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everyone gets a bootram
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2021-03-18 12:35:37 -04:00 |
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Shreya Sanghai
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36f0631203
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added gshare and global history predictor
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2021-03-16 17:03:01 -04:00 |
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Shreya Sanghai
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9eed875886
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added global history branch predictor
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2021-03-16 16:06:40 -04:00 |
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Shreya Sanghai
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74f1641c5a
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Merge branch 'counters' into main
added a configurable number of performance counters
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2021-03-16 11:01:30 -04:00 |
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Ross Thompson
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4c8952de6a
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Converted branch predictor preloads to use system verilog rather than modelsim's load command.
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2021-03-15 12:39:44 -05:00 |
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Thomas Fleming
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1294235837
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
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2021-03-11 00:15:58 -05:00 |
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Ross Thompson
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301166d062
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Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
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2021-03-05 15:23:53 -06:00 |
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Thomas Fleming
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8c97143be6
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Place tlb parameters into constant header file
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2021-03-05 13:35:24 -05:00 |
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Shreya Sanghai
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f0ec365117
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added performance counters
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2021-03-04 11:42:52 -05:00 |
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Brett Mathis
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79cb7ed571
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Parallel FSR's and F CTRL logic
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2021-02-04 02:25:55 -06:00 |
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