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37e6a45d76
cvw
/
wally-pipelined
/
src
/
ieu
History
David Harris
91f6858de7
Merge branch 'main' of
https://github.com/davidharrishmc/riscv-wally
into main
2021-02-02 19:44:43 -05:00
..
alu.sv
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
controller.sv
Moved writeback pipeline registers from datapth into DMEM and CSR
2021-02-02 13:02:31 -05:00
datapath.sv
Minor tweaks
2021-02-02 19:44:37 -05:00
extend.sv
same thing but do that right this time
2021-02-02 21:47:15 +00:00
forward.sv
Moved LoadStall generation to IEU
2021-02-02 13:42:23 -05:00
ieu.sv
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
regfile.sv
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
shifter.sv
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
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