Domenico Ottolia 65abe13f4f Cause an Illegal Instruction Exception when attempting to write readonly CSRs		2021-04-08 05:12:54 -04:00
..
csr.sv	Cause an Illegal Instruction Exception when attempting to write readonly CSRs	2021-04-08 05:12:54 -04:00
csrc.sv	PC counts branch instructions	2021-03-23 14:25:51 -04:00
csri.sv	future work comment about suspicious-looking verilog in csri.sv	2021-03-25 00:10:44 -04:00
csrm.sv	Cause an Illegal Instruction Exception when attempting to write readonly CSRs	2021-04-08 05:12:54 -04:00
csrn.sv	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
csrs.sv	Implement sfence.vma and fix tlb writing	2021-04-01 15:55:05 -04:00
csrsr.sv	busybear: make CSRs only weird for us	2021-03-05 00:46:32 +00:00
csru.sv	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
privdec.sv	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00
privileged.sv	Implement sfence.vma and fix tlb writing	2021-04-01 15:55:05 -04:00
trap.sv	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00