Ross Thompson bc0edc7bdf Updated ila signals. ... Improve fpga wave config. added back in the fpga preload.		2022-08-25 09:03:29 -05:00
..
bootrom.txt	Added bootrom.txt.	2022-03-30 17:29:48 -05:00
dcache-miss-evict-dirty-deadlock.tsm	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
load-deadlock.tsm	Added comport.setup to remind how to configure com port for xilinx fpga.	2022-01-25 14:54:38 -06:00
Makefile	Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.	2021-12-12 17:21:44 -06:00
trigger.tsm	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
wally.tcl	test.	2022-03-28 17:04:58 -05:00
wave_config.wcfg	Updated ila signals.	2022-08-25 09:03:29 -05:00
xlnx_ahblite_axi_bridge.tcl	Updated debug2 ila signal names.	2022-01-28 11:43:49 -06:00
xlnx_axi_clock_converter.tcl	Improved FPGA makefile and fixed timing constraints in clock converter.	2021-12-03 10:05:13 -06:00
xlnx_ddr4.tcl	UART and clock speed changes to support 30Mhz.	2022-04-12 17:56:36 -05:00
xlnx_proc_sys_reset.tcl	Created Makefile to manage IP generation.	2021-11-29 18:33:58 -06:00