cvw/wally-pipelined/src
2021-07-04 12:48:20 -04:00
..
cache src/cache/ICacheCntrl.sv 2021-07-03 11:24:41 -05:00
ebu Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker 2021-07-03 03:29:33 -04:00
fpu Commented out some unused modules 2021-07-04 01:40:27 -04:00
generic Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
hazard Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
ieu Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
ifu Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-04 12:48:20 -04:00
lsu Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries 2021-07-04 11:39:59 -04:00
mmu Replaced generates with arrays in TLB 2021-07-04 12:32:27 -04:00
muldiv Commented out some unused modules 2021-07-04 01:40:27 -04:00
privileged Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-04 12:48:20 -04:00
uncore Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries 2021-07-04 11:39:59 -04:00
wally Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-04 12:48:20 -04:00