This website requires JavaScript.
Explore
Help
Register
Sign In
Xavi
/
cvw
Watch
1
Star
0
Fork
0
You've already forked cvw
forked from
Github_Repos/cvw
Code
Issues
Pull Requests
Packages
Projects
Releases
Wiki
Activity
2d72bed1f4
cvw
/
pipelined
/
regression
History
…
..
slack-notifier
wave-dos
buildrootBugFinder.py
fpga-wave.do
lint-wally
Converted tvecmux to structural
2022-12-20 16:24:04 -08:00
linux-wave.do
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
make-tests.sh
Makefile
makefile-memfile
regression-wally
sim-buildroot
sim-buildroot-batch
sim-testfloat
sim-testfloat-batch
sim-wally
sim-wally-batch
testfloat.do
wally-harvard.do
wally-pipelined-batch.do
wally-pipelined.do
wave-all.do
wave-fpu.do
wave.do
Home