Ross Thompson 42ef1e22e5 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. ... 2. Removed the write address delay from simpleram.sv 3. Fixed rv32tim and rv32ic mode to handle missalignment correctly. 4. Added imperas32i and imperas32c to rv32tim mode.		2022-01-26 18:23:39 -06:00
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cache.sv	LSU Cleanup	2022-01-15 01:11:17 +00:00
cachefsm.sv	1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.	2022-01-26 18:23:39 -06:00
cachereplacementpolicy.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
cacheway.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
dcache_ptw_interaction_README.txt	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sram1rw.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00