Ross Thompson 1f0821da0d IFU and LSU now share the same busdp module.		2022-01-31 16:25:41 -06:00
..
cache	1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.	2022-01-26 18:23:39 -06:00
ebu	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
fpu	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
generic	1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.	2022-01-26 18:23:39 -06:00
hazard	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
ieu	Merged in the debug ila updates.	2022-01-18 17:29:21 -06:00
ifu	IFU and LSU now share the same busdp module.	2022-01-31 16:25:41 -06:00
lsu	partial ifu cleanup.	2022-01-31 16:08:53 -06:00
mmu	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
muldiv	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
privileged	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-31 12:17:37 -06:00
uncore	Comments in LSU code about restructuring	2022-01-27 15:53:59 +00:00
wally	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00