cvw/pipelined/regression
Ross Thompson 91fcca9d17 Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
2022-09-21 12:20:00 -05:00
..
slack-notifier added instructions to slack notifier 2022-05-18 16:50:31 -07:00
wave-dos Added generate around uncore. 2022-08-25 10:35:24 -05:00
wkdir
buildrootBugFinder.py
fpga-wave.do Merged together bram1p1rw with sram1p1rw as sram1p1rw. 2022-09-21 12:20:00 -05:00
lint-wally removed rv64fp from lint 2022-06-21 15:48:47 -07:00
linux-wave.do Merged together bram1p1rw with sram1p1rw as sram1p1rw. 2022-09-21 12:20:00 -05:00
make-tests.sh simplified make-tests.sh to run the current makefile in regression 2022-05-17 17:29:34 -07:00
Makefile More riscof makefile tuning 2022-07-25 21:15:56 +00:00
makefile-memfile plic-s debug 2022-08-03 12:33:09 +00:00
regression-wally Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 12:26:50 -05:00
sim-buildroot
sim-buildroot-batch sim-buildroot-batch now runs wally-pipelined-batch 2022-07-06 18:06:43 -07:00
sim-testfloat Running 16-bit square root cases first in testfloat 2022-09-07 11:11:35 -07:00
sim-testfloat-batch fixed error in divsqrt 2022-07-14 18:16:00 +00:00
sim-wally Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus. 2022-08-27 20:31:09 -07:00
sim-wally-batch Fixed address decoder hanging buildroot 2022-08-26 22:01:25 -07:00
testfloat.do Moved fpu modules into subdirectories 2022-09-20 04:12:05 -07:00
wally-harvard.do
wally-pipelined-batch.do Named change for ahb tests to be less annoying. 2022-09-07 12:24:41 -05:00
wally-pipelined.do Modified regression tests to add some ahb configurations. 2022-09-07 12:03:58 -05:00
wave-all.do Added generate around uncore. 2022-08-25 10:35:24 -05:00
wave-fpu.do Removed unused otfc for Q 2022-09-19 00:43:27 -07:00
wave.do Merged together bram1p1rw with sram1p1rw as sram1p1rw. 2022-09-21 12:20:00 -05:00