cvw/wally-pipelined/config
2021-11-23 10:00:32 -06:00
..
buildroot Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation. 2021-11-23 10:00:32 -06:00
coremark added DESIGN_COMPLIER to forgotten config files 2021-10-12 10:14:04 -07:00
coremark_bare added DESIGN_COMPLIER to forgotten config files 2021-10-12 10:14:04 -07:00
old Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
rv32g made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
rv32ic made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
rv64BP made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
rv64g removed reduntant definitions for FPU in MISA. 2021-10-22 15:18:25 -05:00
rv64ic made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
shared FMA parameterized 2021-07-20 22:04:21 -04:00