forked from Github_Repos/cvw
36 lines
879 B
Systemverilog
36 lines
879 B
Systemverilog
module sbtm_div (input logic [11:0] a, output logic [10:0] ia_out);
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// bit partitions
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logic [3:0] x0;
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logic [2:0] x1;
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logic [3:0] x2;
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logic [2:0] x2_1cmp;
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// mem outputs
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logic [12:0] y0;
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logic [4:0] y1;
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// input to CPA
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logic [14:0] op1;
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logic [14:0] op2;
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logic [14:0] p;
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logic cout;
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assign x0 = a[10:7];
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assign x1 = a[6:4];
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assign x2 = a[3:0];
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sbtm_a0 mem1 ({x0, x1}, y0);
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// 1s cmp per sbtm/stam
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assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0];
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sbtm_a1 mem2 ({x0, x2_1cmp}, y1);
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assign op1 = {1'b0, y0, 1'b0};
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// 1s cmp per sbtm/stam
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assign op2 = x2[3] ? {1'b1, {8{1'b1}}, ~y1, 1'b1} :
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{1'b0, 8'b0, y1, 1'b1};
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// CPA
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// adder #(15) cp1 (op1, op2, 1'b0, p, cout);
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assign {cout, p} = op1 + op2;
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//assign ia_out = {p[14:4], {53{1'b0}}};
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assign ia_out = p[14:4];
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endmodule // sbtm
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