cvw/pipelined/regression
2023-01-29 14:25:28 -08:00
..
slack-notifier
wave-dos
buildrootBugFinder.py
fpga-wave.do Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 2022-12-23 15:10:37 -06:00
lint-wally Converted rv32ic to rv32imc 2023-01-29 11:33:54 -08:00
linux-wave.do Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 2022-12-23 15:10:37 -06:00
make-tests.sh
Makefile Makefile and setup cleanup 2023-01-15 20:27:12 -08:00
makefile-memfile Clean up warnings from Questa 2023-01-17 13:43:39 -08:00
regression-wally Converted rv32ic to rv32imc 2023-01-29 11:33:54 -08:00
sim-buildroot
sim-buildroot-batch
sim-testfloat
sim-testfloat-batch
sim-wally FPU test list 2022-12-01 10:18:36 -08:00
sim-wally-batch Renamed endianswap to match module name 2022-10-04 17:33:49 +00:00
test test 2023-01-20 15:23:38 -08:00
testfloat.do Moved fpu modules into subdirectories 2022-09-20 04:12:05 -07:00
wally-pipelined-batch.do Converted rv32ic to rv32imc 2023-01-29 11:33:54 -08:00
wally-pipelined.do Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
wave-all.do Changing signal name to ImmExtD/E to match figures 2023-01-17 06:33:58 -08:00
wave-fpu.do reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
wave.do Fixed another bug with the speculative gshare with instruction class prediction. 2023-01-29 00:33:40 -06:00