forked from Github_Repos/cvw
198 lines
6.8 KiB
Systemverilog
198 lines
6.8 KiB
Systemverilog
///////////////////////////////////////////
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// srt.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module qsel2 ( // *** eventually just change to 4 bits
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input logic [3:0] ps, pc,
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output logic qp, qz//, qn
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);
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logic [3:0] p, g;
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logic magnitude, sign, cout;
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// The quotient selection logic is presented for simplicity, not
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// for efficiency. You can probably optimize your logic to
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// select the proper divisor with less delay.
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// Qmient equations from EE371 lecture notes 13-20
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assign p = ps ^ pc;
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assign g = ps & pc;
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assign magnitude = ~(&p[2:0]);
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assign cout = g[2] | (p[2] & (g[1] | p[1] & g[0]));
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assign sign = p[3] ^ cout;
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/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) &
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(ps[52]^pc[52]));
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assign #1 sign = (ps[55]^pc[55])^
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(ps[54] & pc[54] | ((ps[54]^pc[54]) &
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(ps[53]&pc[53] | ((ps[53]^pc[53]) &
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(ps[52]&pc[52]))))); */
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// Produce quotient = +1, 0, or -1
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assign qp = magnitude & ~sign;
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assign qz = ~magnitude;
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// assign #1 qn = magnitude & sign;
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endmodule
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////////////////////////////////////
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// Adder Input Generation, Radix 2 //
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////////////////////////////////////
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module fgen2 (
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input logic sp, sz,
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input logic [`DIVb-1:0] C,
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input logic [`DIVb:0] S, SM,
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output logic [`DIVb+3:0] F
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);
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logic [`DIVb+3:0] FP, FN, FZ;
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logic [`DIVb+3:0] SExt, SMExt, CExt;
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assign SExt = {3'b0, S};
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assign SMExt = {3'b0, SM};
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assign CExt = {4'hf, C};
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// Generate for both positive and negative bits
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assign FP = ~(SExt << 1) & CExt;
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assign FN = (SMExt << 1) | (CExt & ~(CExt << 2));
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assign FZ = '0;
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// Choose which adder input will be used
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always_comb
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if (sp) F = FP;
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else if (sz) F = FZ;
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else F = FN;
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endmodule
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module qsel4 (
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input logic [`DIVN-2:0] D,
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input logic [`DIVb+3:0] WS, WC,
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input logic Sqrt,
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output logic [3:0] q
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);
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logic [6:0] Wmsbs;
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logic [7:0] PreWmsbs;
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logic [2:0] Dmsbs;
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assign PreWmsbs = WC[`DIVb+3:`DIVb-4] + WS[`DIVb+3:`DIVb-4];
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assign Wmsbs = PreWmsbs[7:1];
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assign Dmsbs = D[`DIVN-2:`DIVN-4];//|{3{D[`DIVN-2]&Sqrt}};
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// D = 0001.xxx...
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// Dmsbs = | |
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// W = xxxx.xxx...
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// Wmsbs = | |
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logic [3:0] QSel4[1023:0];
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always_comb begin
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integer d, w, i, w2;
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for(d=0; d<8; d++)
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for(w=0; w<128; w++)begin
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i = d*128+w;
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w2 = w-128*(w>=64); // convert to two's complement
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case(d)
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0: if($signed(w2)>=$signed(12)) QSel4[i] = 4'b1000;
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else if(w2>=4) QSel4[i] = 4'b0100;
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else if(w2>=-4) QSel4[i] = 4'b0000;
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else if(w2>=-13) QSel4[i] = 4'b0010;
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else QSel4[i] = 4'b0001;
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1: if(w2>=14) QSel4[i] = 4'b1000;
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else if(w2>=4) QSel4[i] = 4'b0100;
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else if(w2>=-5) QSel4[i] = 4'b0000; // was -6
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else if(~Sqrt&(w2>=-15)) QSel4[i] = 4'b0010; // divide case
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else if( Sqrt&(w2>=-14)) QSel4[i] = 4'b0010; // sqrt case
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else QSel4[i] = 4'b0001;
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2: if(w2>=15) QSel4[i] = 4'b1000;
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else if(w2>=4) QSel4[i] = 4'b0100;
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else if(w2>=-6) QSel4[i] = 4'b0000;
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else if(w2>=-16) QSel4[i] = 4'b0010;
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else QSel4[i] = 4'b0001;
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3: if(w2>=16) QSel4[i] = 4'b1000;
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else if(w2>=4) QSel4[i] = 4'b0100;
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else if(w2>=-6) QSel4[i] = 4'b0000;
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else if(w2>=-17) QSel4[i] = 4'b0010; // was -18
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else QSel4[i] = 4'b0001;
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4: if(w2>=18) QSel4[i] = 4'b1000;
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else if(w2>=6) QSel4[i] = 4'b0100;
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else if(w2>=-6) QSel4[i] = 4'b0000; // was -8
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else if(~Sqrt&(w2>=-20)) QSel4[i] = 4'b0010; // divide case
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else if( Sqrt&(w2>=-18)) QSel4[i] = 4'b0010; // sqrt case
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else QSel4[i] = 4'b0001;
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5: if(w2>=20) QSel4[i] = 4'b1000;
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else if(w2>=6) QSel4[i] = 4'b0100;
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else if(w2>=-8) QSel4[i] = 4'b0000;
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else if(w2>=-20) QSel4[i] = 4'b0010;
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else QSel4[i] = 4'b0001;
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6: if(w2>=20) QSel4[i] = 4'b1000;
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else if(w2>=8) QSel4[i] = 4'b0100;
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else if(w2>=-8) QSel4[i] = 4'b0000;
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else if(w2>=-22) QSel4[i] = 4'b0010;
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else QSel4[i] = 4'b0001;
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7: if(w2>=22) QSel4[i] = 4'b1000; // was 24
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else if(w2>=8) QSel4[i] = 4'b0100;
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else if(w2>=-8) QSel4[i] = 4'b0000;
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else if(w2>=-23) QSel4[i] = 4'b0010; // was -24 ***use -22
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else QSel4[i] = 4'b0001;
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endcase
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end
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end
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assign q = QSel4[{Dmsbs,Wmsbs}];
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endmodule
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////////////////////////////////////
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// Adder Input Generation, Radix 4 //
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////////////////////////////////////
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module fgen4 (
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input logic [3:0] s,
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input logic [`DIVb+3:0] C, S, SM,
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output logic [`DIVb+3:0] F
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);
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logic [`DIVb+3:0] F2, F1, F0, FN1, FN2;
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// Generate for both positive and negative bits
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assign F2 = (~S << 2) & (C << 2);
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assign F1 = ~(S << 1) & C;
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assign F0 = '0;
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assign FN1 = (SM << 1) | (C & ~(C << 3));
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assign FN2 = (SM << 2) | ((C << 2)&~(C << 4));
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// Choose which adder input will be used
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always_comb
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if (s[3]) F = F2;
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else if (s[2]) F = F1;
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else if (s[1]) F = FN1;
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else if (s[0]) F = FN2;
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else F = F0;
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// assign F = sp ? FP : (sn ? FN : FZ);
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endmodule |