forked from Github_Repos/cvw
102 lines
4.4 KiB
Systemverilog
102 lines
4.4 KiB
Systemverilog
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///////////////////////////////////////////
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//
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// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
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// Modified:
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//
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// Purpose: FMA alginment shift
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fmaalign(
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input logic [`NE-1:0] Xe, Ye, Ze, // biased exponents in B(NE.0) format
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input logic [`NF:0] Zm, // significand in U(0.NF) format]
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input logic XZero, YZero, ZZero, // is the input zero
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output logic [3*`NF+5:0] Am, // addend aligned for addition in U(NF+5.2NF+1)
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output logic ZmSticky, // Sticky bit calculated from the aliged addend
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output logic KillProd // should the product be set to zero
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);
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logic [`NE+1:0] ACnt; // how far to shift the addend to align with the product in Q(NE+2.0) format
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logic [4*`NF+5:0] ZmShifted; // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
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logic [4*`NF+5:0] ZmPreshifted; // input to the alignment shifter U(NF+5.3NF+1)
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logic KillZ;
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///////////////////////////////////////////////////////////////////////////////
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// Alignment shifter
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///////////////////////////////////////////////////////////////////////////////
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// determine the shift count for alignment
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// - negitive means Z is larger, so shift Z left
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// - positive means the product is larger, so shift Z right
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// This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed
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assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)} + (`NE+2)'(`NF+3) - {2'b0, Ze};
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// Defualt Addition without shifting
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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// the 1'b0 before the added is because the product's mantissa has two bits before the binary point (xx.xxxxxxxxxx...)
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assign ZmPreshifted = {Zm,(3*`NF+5)'(0)};
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assign KillProd = (ACnt[`NE+1]&~ZZero)|XZero|YZero;
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assign KillZ = $signed(ACnt)>$signed((`NE+2)'(3)*(`NE+2)'(`NF)+(`NE+2)'(5));
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always_comb
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begin
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// If the product is too small to effect the sum, kill the product
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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if (KillProd) begin
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ZmShifted = {(`NF+3)'(0), Zm, (2*`NF+2)'(0)};
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ZmSticky = ~(XZero|YZero);
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// If the addend is too small to effect the addition
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// - The addend has to shift two past the end of the addend to be considered too small
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// - The 2 extra bits are needed for rounding
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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end else if (KillZ) begin
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ZmShifted = 0;
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ZmSticky = ~ZZero;
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// If the Addend is shifted right
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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end else begin
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ZmShifted = ZmPreshifted >> ACnt;
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ZmSticky = |(ZmShifted[`NF-1:0]);
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end
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end
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assign Am = ZmShifted[4*`NF+5:`NF];
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endmodule
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