forked from Github_Repos/cvw
a75d7e4555
So I'm super sorry for accidently overwriting the commits this morning Need to be more careful with force pushing :( This fixes the problem with CSRR somehow, by tying InstrAccessFaultF and DataAccessFaultM to zero for now. I feel like this is not a good solution and will cause problems in the future, but for the start it seems to work for now. I'm fair certain we need these to accurately simulate to do linux properly. Anyway, this super hackish solution is in place for now, now on to ignoring mispredicted reads
127 lines
4.7 KiB
Plaintext
127 lines
4.7 KiB
Plaintext
# wally-pipelined.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with testbench_busybear
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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}
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vlib work
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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vlog src/*.sv -suppress 2583
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc work.testbench_busybear -o workopt
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vsim workopt
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view wave
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-- display input and output signals as hexidecimal values
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# Diplays All Signals recursively
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add wave /testbench_busybear/clk
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add wave /testbench_busybear/reset
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add wave -divider
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add wave -hex /testbench_busybear/pcExpected
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add wave -hex /testbench_busybear/dut/dp/PCF
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add wave -hex /testbench_busybear/dut/dp/InstrF
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add wave -divider
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# registers!
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add wave -hex /testbench_busybear/rfExpected
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add wave -hex /testbench_busybear/dut/dp/regf/rf[1]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[2]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[3]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[4]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[5]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[6]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[7]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[8]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[9]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[10]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[11]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[12]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[13]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[14]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[15]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[16]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[17]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[18]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[19]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[20]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[21]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[22]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[23]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[24]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[25]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[26]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[27]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[28]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[29]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[30]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[31]
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add wave /testbench_busybear/InstrFName
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add wave -hex /testbench_busybear/dut/dp/PCD
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#add wave -hex /testbench_busybear/dut/dp/InstrD
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add wave /testbench_busybear/InstrDName
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#add wave -divider
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add wave -hex /testbench_busybear/dut/dp/PCE
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##add wave -hex /testbench_busybear/dut/dp/InstrE
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add wave /testbench_busybear/InstrEName
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#add wave -hex /testbench_busybear/dut/dp/SrcAE
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#add wave -hex /testbench_busybear/dut/dp/SrcBE
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#add wave -hex /testbench_busybear/dut/dp/ALUResultE
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#add wave /testbench_busybear/dut/dp/PCSrcE
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#add wave -divider
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add wave -hex /testbench_busybear/dut/dp/PCM
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##add wave -hex /testbench_busybear/dut/dp/InstrM
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add wave /testbench_busybear/InstrMName
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#add wave /testbench_busybear/dut/dmem/dtim/memwrite
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#add wave -hex /testbench_busybear/dut/dmem/AdrM
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#add wave -hex /testbench_busybear/dut/dmem/WriteDataM
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#add wave -divider
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add wave -hex /testbench_busybear/dut/dp/PCW
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##add wave -hex /testbench_busybear/dut/dp/InstrW
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add wave /testbench_busybear/InstrWName
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#add wave /testbench_busybear/dut/dp/RegWriteW
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#add wave -hex /testbench_busybear/dut/dp/ResultW
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#add wave -hex /testbench_busybear/dut/dp/RdW
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#add wave -divider
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##add ww
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#add wave -hex -r /testbench_busybear/*
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#
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#-- Set Wave Output Items
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#TreeUpdate [SetDefaultTree]
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#WaveRestoreZoom {0 ps} {100 ps}
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#configure wave -namecolwidth 250
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#configure wave -valuecolwidth 120
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#configure wave -justifyvalue left
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#configure wave -signalnamewidth 0
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#configure wave -snapdistance 10
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#configure wave -datasetprefix 0
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#configure wave -rowmargin 4
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#configure wave -childrowmargin 2
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#set DefaultRadix hexadecimal
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#
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#-- Run the Simulation
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run 300
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#run -all
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##quit
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