So I'm super sorry for accidently overwriting the commits this morning
Need to be more careful with force pushing :(
This fixes the problem with CSRR somehow, by tying InstrAccessFaultF and
DataAccessFaultM to zero for now. I feel like this is not a good solution
and will cause problems in the future, but for the start it seems to work for now.
I'm fair certain we need these to accurately simulate to do linux properly.
Anyway, this super hackish solution is in place for now, now on to ignoring mispredicted reads
fixes the python parser:
get the value, not function name, of PC
only write changes to registers instead of registers every cycle
temporarilly NOP out CSRR instruction (with the canonical NOP), that was breaking this
dont stop on errors, print them prettier
- Copy bare-bones testbench from E85
- have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier
- Create .gitignore for vsim files
- Make PC reset a macro, change to 0x1000 to conform to the bootloader
I don't know a good way to put the linux register trace file we're generating on git,
since its both nontrivial to make and way to big to keep in a git repo
for now it lives in /mnt/scratch/riscv_testbench/
