Ross Thompson 7f62808544 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main		2021-07-04 16:19:39 -05:00
..
adrdec.sv	Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.	2021-06-24 19:59:29 -04:00
adrdecs.sv	Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.	2021-07-04 01:19:38 -04:00
decoder.sv	remove redundant decodes, fixed mmu logic ins/outs	2021-06-07 19:23:30 -04:00
mmu.sv	Fixed MPRV and MXR checks in TLB	2021-07-04 13:20:29 -04:00
pagetablewalker.sv	removed mmustall and finished port annotations on ptw and lsuArb.	2021-07-03 16:06:09 -05:00
pmachecker.sv	Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.	2021-07-04 01:19:38 -04:00
pmpadrdec.sv	Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker	2021-07-03 03:29:33 -04:00
pmpchecker.sv	Replaced generates with arrays in TLB	2021-07-04 12:32:27 -04:00
tlb.sv	Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders	2021-07-04 16:33:13 -04:00
tlbcam.sv	Restructured TLB Read as AND-OR operation with one-hot match/read line	2021-07-04 17:01:22 -04:00
tlbcamline.sv	Restructured TLB Read as AND-OR operation with one-hot match/read line	2021-07-04 17:01:22 -04:00
tlblru.sv	Restructured TLB Read as AND-OR operation with one-hot match/read line	2021-07-04 17:01:22 -04:00
tlbphysicalpagemask.sv	TLB cleanup	2021-07-04 14:59:04 -04:00
tlbpriority.sv	Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders	2021-07-04 16:33:13 -04:00
tlbram.sv	Restructured TLB Read as AND-OR operation with one-hot match/read line	2021-07-04 17:01:22 -04:00
tlbramline.sv	Restructured TLB Read as AND-OR operation with one-hot match/read line	2021-07-04 17:01:22 -04:00