eroom1966 0d260accb4 Fix MISA RO and UART addresses ... It appears on inspection that the MISA register is read only in Wally In which case this has now also been set in the ImperasDV representation Also the Addresss for the UART R/W privileges are corrected		2023-03-13 11:07:19 +00:00
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common	Add support for setting PMP registers	2023-03-08 12:44:53 +00:00
fp	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00
sdc	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00
testbench_imperas.sv	Fix MISA RO and UART addresses	2023-03-13 11:07:19 +00:00
testbench-fp.sv	Fixed license on testbench files	2023-02-04 08:19:20 -08:00
testbench-linux.sv	Fixed license on testbench files	2023-02-04 08:19:20 -08:00
testbench.sv	Updated testbench to record coremark performance counters.	2023-03-08 17:11:27 -06:00
tests-fp.vh	Fixed license on testbench files	2023-02-04 08:19:20 -08:00
tests.vh	Fixed another bug in the btb.	2023-02-20 17:54:22 -06:00