forked from Github_Repos/cvw
128 lines
5.2 KiB
Systemverilog
128 lines
5.2 KiB
Systemverilog
///////////////////////////////////////////
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// tlb.sv
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//
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// Written: jtorrey@hmc.edu 16 February 2021
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// Modified: kmacsaigoren@hmc.edu 1 June 2021
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// Implemented SV48 on top of SV39. This included adding the SvMode signal,
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// and using it to decide the translate signal and get the virtual page number
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//
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// Purpose: Translation lookaside buffer
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// Cache of virtural-to-physical address translations
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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/**
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* SV32 specs
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* ----------
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* Virtual address [31:0] (32 bits)
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* [________________________________]
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* |--VPN1--||--VPN0--||----OFF---|
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* 10 10 12
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*
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* Physical address [33:0] (34 bits)
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* [__________________________________]
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* |---PPN1---||--PPN0--||----OFF---|
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* 12 10 12
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*
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* Page Table Entry [31:0] (32 bits)
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* [________________________________]
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* |---PPN1---||--PPN0--|||DAGUXWRV
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* 12 10 ^^
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* RSW(2) -- for OS
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*/
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`include "wally-config.vh"
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// The TLB will have 2**ENTRY_BITS total entries
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module tlb #(parameter TLB_ENTRIES = 8,
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parameter ITLB = 0) (
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input logic clk, reset,
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// Current value of satp CSR (from privileged unit)
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input logic [`SVMODE_BITS-1:0] SATP_MODE,
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input logic [`ASID_BITS-1:0] SATP_ASID,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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// Current privilege level of the processeor
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input logic [1:0] PrivilegeModeW,
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// 00 - TLB is not being accessed
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// 1x - TLB is accessed for a read (or an instruction)
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// x1 - TLB is accessed for a write
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// 11 - TLB is accessed for both read and write
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input logic ReadAccess, WriteAccess,
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input logic DisableTranslation,
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// address input before translation (could be physical or virtual)
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input logic [`XLEN-1:0] Address,
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// Controls for writing a new entry to the TLB
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input logic [`XLEN-1:0] PTE,
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input logic [1:0] PageTypeWriteVal,
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input logic TLBWrite,
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// Invalidate all TLB entries
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input logic TLBFlush,
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// Physical address outputs
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output logic [`PA_BITS-1:0] TLBPAdr,
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output logic TLBMiss,
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output logic TLBHit,
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output logic Translate,
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// Faults
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output logic TLBPageFault
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);
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logic [TLB_ENTRIES-1:0] Matches, WriteEnables, PTE_Gs; // used as the one-hot encoding of WriteIndex
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// Sections of the virtual and physical addresses
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logic [`VPN_BITS-1:0] VPN;
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logic [`PPN_BITS-1:0] PPN;
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logic [`XLEN+1:0] AddressExt;
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// Sections of the page table entry
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logic [7:0] PTEAccessBits;
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logic [11:0] PageOffset;
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logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
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logic [1:0] HitPageType;
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logic CAMHit;
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logic SV39Mode;
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assign VPN = Address[`VPN_BITS+11:12];
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tlbcontrol tlbcontrol(.SATP_MODE, .Address, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
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.PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault,
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.SV39Mode, .Translate);
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tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables);
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tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS)
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tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs,
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.SATP_ASID, .Matches, .HitPageType, .CAMHit);
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tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PPN, .PTEAccessBits, .PTE_Gs);
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// Replace segments of the virtual page number with segments of the physical
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// page number. For 4 KB pages, the entire virtual page number is replaced.
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// For superpages, some segments are considered offsets into a larger page.
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tlbmixer Mixer(.VPN, .PPN, .HitPageType, .Address(Address[11:0]), .TLBHit, .TLBPAdr);
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endmodule
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