Ross Thompson 3b31d8f8fb Updated debug2 ila signal names.		2022-01-28 11:43:49 -06:00
..
dcache-miss-evict-dirty-deadlock.tsm	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
load-deadlock.tsm	Added comport.setup to remind how to configure com port for xilinx fpga.	2022-01-25 14:54:38 -06:00
Makefile	Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.	2021-12-12 17:21:44 -06:00
trigger.tsm	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
wally.tcl	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
xlnx_ahblite_axi_bridge.tcl	Updated debug2 ila signal names.	2022-01-28 11:43:49 -06:00
xlnx_axi_clock_converter.tcl	Improved FPGA makefile and fixed timing constraints in clock converter.	2021-12-03 10:05:13 -06:00
xlnx_ddr4.tcl	Oups missed files in the last commit.	2021-12-15 10:25:08 -06:00
xlnx_proc_sys_reset.tcl	Created Makefile to manage IP generation.	2021-11-29 18:33:58 -06:00