forked from Github_Repos/cvw
113 lines
4.9 KiB
Systemverilog
113 lines
4.9 KiB
Systemverilog
///////////////////////////////////////////
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// tlbcamline.sv
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//
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// Written: tfleming@hmc.edu & jtorrey@hmc.edu 6 April 2021
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// Modified: kmacsaigoren@hmc.edu 1 June 2021
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// Implemented SV48 on top of SV39. This included adding SvMode input signal and the wally constants
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// Mostly this was done to make the PageNumberMixer work.
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//
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// Purpose: CAM line for the translation lookaside buffer (TLB)
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// Determines whether a virtual page number matches the stored key.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module tlbcamline #(parameter KEY_BITS = 20,
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parameter SEGMENT_BITS = 10) (
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input logic clk, reset,
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// input to check which SvMode is running
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// input logic [`SVMODE_BITS-1:0] SvMode, // *** may no longer be needed.
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// The requested page number to compare against the key
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input logic [KEY_BITS-1:0] VirtualPageNumber,
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// Signals to write a new entry to this line
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input logic WriteEnable,
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input logic [1:0] PageTypeWriteVal,
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// Flush this line (set valid to 0)
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input logic TLBFlush,
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// This entry is a key for a tera, giga, mega, or kilopage.
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// PageType == 2'b00 --> kilopage
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// PageType == 2'b01 --> megapage
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// PageType == 2'b10 --> gigapage
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// PageType == 2'b11 --> terapage
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output logic [1:0] PageTypeRead, // *** should this be the stored version or the always updated one?
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output logic Match
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);
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// This entry has KEY_BITS for the key plus one valid bit.
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logic Valid;
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logic [KEY_BITS-1:0] Key;
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logic [1:0] PageType;
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// Split up key and query into sections for each page table level.
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logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1;
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logic Match0, Match1;
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// *** need to add ASID and G bit support
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generate
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if (`XLEN == 32) begin
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assign {Key1, Key0} = Key;
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assign {Query1, Query0} = VirtualPageNumber;
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// Calculate the actual match value based on the input vpn and the page type.
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// For example, a megapage in SV32 only cares about VPN[1], so VPN[0]
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// should automatically match.
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assign Match0 = (Query0 == Key0) || (PageType[0]); // least signifcant section
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assign Match1 = (Query1 == Key1);
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assign Match = Match0 & Match1 & Valid;
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end else begin
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logic [SEGMENT_BITS-1:0] Key2, Key3, Query2, Query3;
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logic Match2, Match3;
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assign {Query3, Query2, Query1, Query0} = VirtualPageNumber;
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assign {Key3, Key2, Key1, Key0} = Key;
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// Calculate the actual match value based on the input vpn and the page type.
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// For example, a gigapage in SV39 only cares about VPN[2], so VPN[0] and VPN[1]
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// should automatically match.
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assign Match0 = (Query0 == Key0) || (PageType > 2'd0); // least signifcant section
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assign Match1 = (Query1 == Key1) || (PageType > 2'd1);
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assign Match2 = (Query2 == Key2) || (PageType > 2'd2);
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assign Match3 = (Query3 == Key3); // this should always match in sv39 since both vPN3 and key3 are zeroed by the pagetable walker before getting to the cam
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assign Match = Match0 & Match1 & Match2 & Match3 & Valid;
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end
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endgenerate
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// On a write, update the type of the page referred to by this line.
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flopenr #(2) pagetypeflop(clk, reset, WriteEnable, PageTypeWriteVal, PageType);
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assign PageTypeRead = PageType & {2{Match}};
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// On a write, set the valid bit high and update the stored key.
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// On a flush, zero the valid bit and leave the key unchanged.
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// *** Might we want to update stored key right away to output match on the
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// write cycle? (using a mux)
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flopenrc #(1) validbitflop(clk, reset, TLBFlush, WriteEnable, 1'b1, Valid);
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flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, VirtualPageNumber, Key);
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endmodule
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