forked from Github_Repos/cvw
157 lines
3.4 KiB
ArmAsm
157 lines
3.4 KiB
ArmAsm
// -----------
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// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
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// version : 0.5.1
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// timestamp : Mon Aug 2 08:58:53 2021 GMT
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// usage : riscv_ctg \
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// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
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// --base-isa rv32e \
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// --randomize
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// -----------
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//
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// -----------
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// Copyright (c) 2020. RISC-V International. All rights reserved.
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the jal instruction of the RISC-V E extension for the jal covergroup.
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//
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#define RVTEST_E
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV32E")
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",jal)
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RVTEST_SIGBASE( x7,signature_x7_1)
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inst_0:
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// rd==x8, imm_val < 0,
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// opcode: jal; dest:x8; immval:0x4; align:0
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TEST_JAL_OP(x2, x8, 0x4, 1b, x7, 0,0)
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inst_1:
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// rd==x14, imm_val == ((2**(18))), imm_val > 0
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// opcode: jal; dest:x14; immval:0x40000; align:0
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TEST_JAL_OP(x2, x14, 0x40000, 3f, x7, 4,0)
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inst_2:
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// rd==x9, imm_val == (-(2**(18))),
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// opcode: jal; dest:x9; immval:0x40000; align:0
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TEST_JAL_OP(x2, x9, 0x40000, 1b, x7, 8,0)
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inst_3:
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// rd==x12,
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// opcode: jal; dest:x12; immval:0x80000; align:0
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TEST_JAL_OP(x2, x12, 0x80000, 1b, x7, 12,0)
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inst_4:
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// rd==x0,
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// opcode: jal; dest:x0; immval:0x80000; align:0
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TEST_JAL_OP(x2, x0, 0x80000, 1b, x7, 16,0)
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inst_5:
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// rd==x3,
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// opcode: jal; dest:x3; immval:0x80000; align:0
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TEST_JAL_OP(x2, x3, 0x80000, 1b, x7, 20,0)
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inst_6:
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// rd==x4,
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// opcode: jal; dest:x4; immval:0x80000; align:0
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TEST_JAL_OP(x2, x4, 0x80000, 1b, x7, 24,0)
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inst_7:
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// rd==x5,
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// opcode: jal; dest:x5; immval:0x80000; align:0
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TEST_JAL_OP(x2, x5, 0x80000, 1b, x7, 28,0)
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inst_8:
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// rd==x13,
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// opcode: jal; dest:x13; immval:0x80000; align:0
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TEST_JAL_OP(x2, x13, 0x80000, 1b, x7, 32,0)
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inst_9:
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// rd==x6,
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// opcode: jal; dest:x6; immval:0x80000; align:0
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TEST_JAL_OP(x2, x6, 0x80000, 1b, x7, 36,0)
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inst_10:
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// rd==x15,
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// opcode: jal; dest:x15; immval:0x80000; align:0
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TEST_JAL_OP(x2, x15, 0x80000, 1b, x7, 40,0)
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inst_11:
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// rd==x1,
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// opcode: jal; dest:x1; immval:0x80000; align:0
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TEST_JAL_OP(x2, x1, 0x80000, 1b, x7, 44,0)
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inst_12:
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// rd==x2,
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// opcode: jal; dest:x2; immval:0x80000; align:0
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TEST_JAL_OP(x3, x2, 0x80000, 1b, x7, 48,0)
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RVTEST_SIGBASE( x1,signature_x1_0)
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inst_13:
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// rd==x7,
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// opcode: jal; dest:x7; immval:0x80000; align:0
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TEST_JAL_OP(x3, x7, 0x80000, 1b, x1, 0,0)
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inst_14:
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// rd==x10,
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// opcode: jal; dest:x10; immval:0x80000; align:0
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TEST_JAL_OP(x3, x10, 0x80000, 1b, x1, 4,0)
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inst_15:
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// rd==x11,
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// opcode: jal; dest:x11; immval:0x80000; align:0
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TEST_JAL_OP(x3, x11, 0x80000, 1b, x1, 8,0)
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#endif
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RVTEST_CODE_END
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RVMODEL_HALT
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RVTEST_DATA_BEGIN
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.align 4
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rvtest_data:
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.word 0xbabecafe
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RVTEST_DATA_END
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RVMODEL_DATA_BEGIN
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signature_x7_0:
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.fill 0*(XLEN/32),4,0xdeadbeef
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signature_x7_1:
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.fill 13*(XLEN/32),4,0xdeadbeef
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signature_x1_0:
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.fill 3*(XLEN/32),4,0xdeadbeef
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#ifdef rvtest_mtrap_routine
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mtrap_sigptr:
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.fill 64*(XLEN/32),4,0xdeadbeef
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#endif
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#ifdef rvtest_gpr_save
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gpr_save:
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.fill 32*(XLEN/32),4,0xdeadbeef
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#endif
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RVMODEL_DATA_END
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