// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.5.1
// timestamp : Mon Aug  2 08:58:53 2021 GMT
// usage     : riscv_ctg \
//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
//                  --base-isa rv32e \
//                  --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the jal instruction of the RISC-V E extension for the jal covergroup.
// 
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",jal)

RVTEST_SIGBASE( x7,signature_x7_1)

inst_0:
// rd==x8, imm_val < 0, 
// opcode: jal; dest:x8; immval:0x4; align:0
TEST_JAL_OP(x2, x8, 0x4, 1b, x7, 0,0)

inst_1:
// rd==x14, imm_val == ((2**(18))), imm_val > 0
// opcode: jal; dest:x14; immval:0x40000; align:0
TEST_JAL_OP(x2, x14, 0x40000, 3f, x7, 4,0)

inst_2:
// rd==x9, imm_val == (-(2**(18))), 
// opcode: jal; dest:x9; immval:0x40000; align:0
TEST_JAL_OP(x2, x9, 0x40000, 1b, x7, 8,0)

inst_3:
// rd==x12, 
// opcode: jal; dest:x12; immval:0x80000; align:0
TEST_JAL_OP(x2, x12, 0x80000, 1b, x7, 12,0)

inst_4:
// rd==x0, 
// opcode: jal; dest:x0; immval:0x80000; align:0
TEST_JAL_OP(x2, x0, 0x80000, 1b, x7, 16,0)

inst_5:
// rd==x3, 
// opcode: jal; dest:x3; immval:0x80000; align:0
TEST_JAL_OP(x2, x3, 0x80000, 1b, x7, 20,0)

inst_6:
// rd==x4, 
// opcode: jal; dest:x4; immval:0x80000; align:0
TEST_JAL_OP(x2, x4, 0x80000, 1b, x7, 24,0)

inst_7:
// rd==x5, 
// opcode: jal; dest:x5; immval:0x80000; align:0
TEST_JAL_OP(x2, x5, 0x80000, 1b, x7, 28,0)

inst_8:
// rd==x13, 
// opcode: jal; dest:x13; immval:0x80000; align:0
TEST_JAL_OP(x2, x13, 0x80000, 1b, x7, 32,0)

inst_9:
// rd==x6, 
// opcode: jal; dest:x6; immval:0x80000; align:0
TEST_JAL_OP(x2, x6, 0x80000, 1b, x7, 36,0)

inst_10:
// rd==x15, 
// opcode: jal; dest:x15; immval:0x80000; align:0
TEST_JAL_OP(x2, x15, 0x80000, 1b, x7, 40,0)

inst_11:
// rd==x1, 
// opcode: jal; dest:x1; immval:0x80000; align:0
TEST_JAL_OP(x2, x1, 0x80000, 1b, x7, 44,0)

inst_12:
// rd==x2, 
// opcode: jal; dest:x2; immval:0x80000; align:0
TEST_JAL_OP(x3, x2, 0x80000, 1b, x7, 48,0)
RVTEST_SIGBASE( x1,signature_x1_0)

inst_13:
// rd==x7, 
// opcode: jal; dest:x7; immval:0x80000; align:0
TEST_JAL_OP(x3, x7, 0x80000, 1b, x1, 0,0)

inst_14:
// rd==x10, 
// opcode: jal; dest:x10; immval:0x80000; align:0
TEST_JAL_OP(x3, x10, 0x80000, 1b, x1, 4,0)

inst_15:
// rd==x11, 
// opcode: jal; dest:x11; immval:0x80000; align:0
TEST_JAL_OP(x3, x11, 0x80000, 1b, x1, 8,0)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END

RVMODEL_DATA_BEGIN


signature_x7_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x7_1:
    .fill 13*(XLEN/32),4,0xdeadbeef


signature_x1_0:
    .fill 3*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

RVMODEL_DATA_END