forked from Github_Repos/cvw
177 lines
8.0 KiB
Systemverilog
Executable File
177 lines
8.0 KiB
Systemverilog
Executable File
///////////////////////////////////////////
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//
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// Written: James Stine
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// Modified: 8/1/2018
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//
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// Purpose: Convergence unit for pipelined floating point divider/square root top unit (Goldschmidt)
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_out,
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regr_out, d, n, sel_muxa, sel_muxb, sel_muxr, reset, clk,
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load_rega, load_regb, load_regc, load_regd, load_regr, load_regs, load_regp,
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P, op_type, exp_odd);
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input logic [52:0] d, n;
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input logic [2:0] sel_muxa, sel_muxb;
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input logic sel_muxr;
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input logic load_rega, load_regb, load_regc, load_regd;
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input logic load_regr, load_regs;
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input logic load_regp;
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input logic P;
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input logic op_type;
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input logic exp_odd;
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input logic reset;
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input logic clk;
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output logic [59:0] q1, qp1, qm1;
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output logic [59:0] q0, qp0, qm0;
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output logic [59:0] rega_out, regb_out, regc_out, regd_out;
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output logic [119:0] regr_out;
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supply1 vdd;
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supply0 vss;
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logic [59:0] muxa_out, muxb_out;
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logic muxr_out;
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logic [10:0] ia_div, ia_sqrt;
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logic [59:0] ia_out;
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logic [119:0] mul_out;
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logic [59:0] q_out1, qm_out1, qp_out1;
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logic [59:0] q_out0, qm_out0, qp_out0;
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logic [59:0] mcand, mplier, mcand_q;
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logic [59:0] twocmp_out;
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logic [60:0] three;
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logic [119:0] Carry, Carry2;
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logic [119:0] Sum, Sum2;
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logic [119:0] constant, constant2;
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logic [59:0] q_const, qp_const, qm_const;
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logic [59:0] d2, n2;
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logic [11:0] d3;
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// Check if exponent is odd for sqrt
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// If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA
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assign d2 = (exp_odd&op_type) ? {vss, d, 6'h0} : {d, 7'h0};
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assign n2 = op_type ? d2 : {n, 7'h0};
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// IA div/sqrt
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sbtm_div ia1 (d[52:41], ia_div);
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sbtm_sqrt ia2 (d2[59:48], ia_sqrt);
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assign ia_out = op_type ? {ia_sqrt, {49{1'b0}}} : {ia_div, {49{1'b0}}};
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// Choose IA or iteration
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mux6 #(60) mx1 (d2, ia_out, rega_out, regc_out, regd_out, regb_out, sel_muxb, muxb_out);
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mux5 #(60) mx2 (regc_out, n2, ia_out, regb_out, regd_out, sel_muxa, muxa_out);
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// Deal with remainder if [0.5, 1) instead of [1, 2)
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mux2 #(120) mx3a ({~n, {67{1'b1}}}, {{1'b1}, ~n, {66{1'b1}}}, q1[59], constant2);
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// Select Mcand, Remainder/Q''
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mux2 #(120) mx3 (120'h0, constant2, sel_muxr, constant);
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// Select mcand - remainder should always choose q1 [1,2) because
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// adjustment of N in the from XX.FFFFFFF
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mux2 #(60) mx4 (q0, q1, q1[59], mcand_q);
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mux2 #(60) mx5 (muxb_out, mcand_q, sel_muxr&op_type, mplier);
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mux2 #(60) mx6 (muxa_out, mcand_q, sel_muxr, mcand);
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// R4 Booth TDM multiplier (carry/save)
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redundantmul #(60) bigmul(.a(mcand), .b(mplier), .out0(Sum), .out1(Carry));
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// Q*D - N (reversed but changed in rounder.v to account for sign reversal)
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csa #(120) csa1 (Sum, Carry, constant, Sum2, Carry2);
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// Add ulp for subtraction in remainder
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mux2 #(1) mx7 (1'b0, 1'b1, sel_muxr, muxr_out);
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// Constant for Q''
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mux2 #(60) mx8 ({60'h0000_0000_0000_020}, {60'h0000_0040_0000_000}, P, q_const);
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mux2 #(60) mx9 ({60'h0000_0000_0000_0A0}, {60'h0000_0140_0000_000}, P, qp_const);
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mux2 #(60) mxA ({60'hFFFF_FFFF_FFFF_F9F}, {60'hFFFF_FF3F_FFFF_FFF}, P, qm_const);
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logic [119:0] Sum_pipe;
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logic [119:0] Carry_pipe;
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logic muxr_pipe;
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logic rega_pipe;
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logic regb_pipe;
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logic regc_pipe;
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logic regd_pipe;
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logic regs_pipe;
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logic regs_pipe2;
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logic regr_pipe;
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logic P_pipe;
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logic op_type_pipe;
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logic [59:0] q_const_pipe;
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logic [59:0] qm_const_pipe;
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logic [59:0] qp_const_pipe;
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logic [59:0] q_const_pipe2;
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logic [59:0] qm_const_pipe2;
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logic [59:0] qp_const_pipe2;
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// Stage 1
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flopenr #(120) regp1 (clk, reset, load_regp, Sum2, Sum_pipe);
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flopenr #(120) regp2 (clk, reset, load_regp, Carry2, Carry_pipe);
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flopenr #(1) regp3 (clk, reset, load_regp, muxr_out, muxr_pipe);
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flopenr #(1) regp4 (clk, reset, load_regp, load_rega, rega_pipe);
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flopenr #(1) regp5 (clk, reset, load_regp, load_regb, regb_pipe);
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flopenr #(1) regp6 (clk, reset, load_regp, load_regc, regc_pipe);
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flopenr #(1) regp7 (clk, reset, load_regp, load_regd, regd_pipe);
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flopenr #(1) regp8 (clk, reset, load_regp, load_regs, regs_pipe);
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flopenr #(1) regp9 (clk, reset, load_regp, load_regr, regr_pipe);
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flopenr #(1) regpA (clk, reset, load_regp, P, P_pipe);
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flopenr #(1) regpB (clk, reset, load_regp, op_type, op_type_pipe);
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flopenr #(60) regpC (clk, reset, load_regp, q_const, q_const_pipe);
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flopenr #(60) regpD (clk, reset, load_regp, qp_const, qp_const_pipe);
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flopenr #(60) regpE (clk, reset, load_regp, qm_const, qm_const_pipe);
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// CPA (from CSA)/Remainder addition/subtraction
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assign mul_out = Sum_pipe + Carry_pipe + {119'h0, muxr_pipe};
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// One's complement instead of two's complement (for hw efficiency)
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assign three = {~mul_out[118] , mul_out[118], ~mul_out[117:59]};
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mux2 #(60) mxTC (~mul_out[118:59], three[60:1], op_type_pipe, twocmp_out);
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// Stage 2
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flopenr #(60) regc (clk, reset, regc_pipe, twocmp_out, regc_out);
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flopenr #(60) regb (clk, reset, regb_pipe, mul_out[118:59], regb_out);
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flopenr #(60) rega (clk, reset, rega_pipe, mul_out[118:59], rega_out);
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flopenr #(60) regd (clk, reset, regd_pipe, mul_out[118:59], regd_out);
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flopenr #(120) regr (clk, reset, regr_pipe, mul_out, regr_out);
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flopenr #(1) regl (clk, reset, regs_pipe, regs_pipe, regs_pipe2);
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flopenr #(60) regm (clk, reset, regs_pipe, q_const_pipe, q_const_pipe2);
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flopenr #(60) regn (clk, reset, regs_pipe, qp_const_pipe, qp_const_pipe2);
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flopenr #(60) rego (clk, reset, regs_pipe, qm_const_pipe, qm_const_pipe2);
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// Assuming [1,2) - q1
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assign q_out1 = regb_out + q_const;
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assign qp_out1 = regb_out + qp_const;
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assign qm_out1 = regb_out + qm_const + 1'b1;
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// Assuming [0.5,1) - q0
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assign q_out0 = {regb_out[58:0], 1'b0} + q_const;
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assign qp_out0 = {regb_out[58:0], 1'b0} + qp_const;
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assign qm_out0 = {regb_out[58:0], 1'b0} + qm_const + 1'b1;
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// Stage 3
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// Assuming [1,2)
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flopenr #(60) rege (clk, reset, regs_pipe2, {q_out1[59:35], (q_out1[34:6] & {29{~P_pipe}}), 6'h0}, q1);
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flopenr #(60) regf (clk, reset, regs_pipe2, {qm_out1[59:35], (qm_out1[34:6] & {29{~P_pipe}}), 6'h0}, qm1);
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flopenr #(60) regg (clk, reset, regs_pipe2, {qp_out1[59:35], (qp_out1[34:6] & {29{~P_pipe}}), 6'h0}, qp1);
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// Assuming [0,1)
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flopenr #(60) regh (clk, reset, regs_pipe2, {q_out0[59:35], (q_out0[34:6] & {29{~P_pipe}}), 6'h0}, q0);
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flopenr #(60) regj (clk, reset, regs_pipe2, {qm_out0[59:35], (qm_out0[34:6] & {29{~P_pipe}}), 6'h0}, qm0);
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flopenr #(60) regk (clk, reset, regs_pipe2, {qp_out0[59:35], (qp_out0[34:6] & {29{~P_pipe}}), 6'h0}, qp0);
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endmodule // divconv
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