David Harris dda035891a PIPELINE test running		2021-11-01 12:44:35 -07:00
..
adderparts.sv	rename adder in fpu for synthesis	2021-10-08 17:47:54 -05:00
cla12.sv	fpu cleanup	2021-07-24 14:59:57 -04:00
cla52.sv	Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.	2021-10-23 06:15:26 -07:00
cla64.sv	fpu cleanup	2021-07-24 14:59:57 -04:00
convert_inputs_div.sv	fpu cleanup	2021-07-24 14:59:57 -04:00
convert_inputs.sv	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
cvtfp.sv	cvtfp module documented	2021-10-14 15:25:31 -07:00
divconv_pipe.sv	Lint cleanup	2021-10-23 09:58:52 -07:00
divconv.sv	Fix fpdivsqrt lint error on CPA for convergence	2021-10-20 17:46:13 -05:00
exception_div.sv	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
exception.sv	all fpu units use the unpacking unit	2021-07-28 23:49:21 -04:00
faddcvt.sv	LZA added to FMA and attemting a merged FMA and adder in synthesis	2021-08-10 13:57:16 -04:00
fclassify.sv	fpu cleanup	2021-07-24 14:59:57 -04:00
fcmp.sv	lint cleanup: FPU and privileged	2021-10-23 09:41:24 -07:00
fctrl.sv	lint warnings fixed	2021-10-12 09:45:02 -07:00
fcvt.sv	lint warnings fixed	2021-10-12 09:45:02 -07:00
fhazard.sv	lint warnings fixed	2021-10-12 09:45:02 -07:00
fma.sv	random lint cleanup	2021-10-23 11:24:36 -07:00
fpdiv_pipe.sv	Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking	2021-10-22 13:41:50 -05:00
fpdiv.sv	Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.	2021-10-20 12:00:41 -05:00
fpu.sv	Fixed FResultSelM to select proper flags	2021-10-27 11:02:42 -07:00
fpudivsqrtrecur.sv	PIPELINE test running	2021-11-01 12:44:35 -07:00
fpudivsqrtrecurcore.sv	Modified rxfull determination in UART, started division	2021-09-12 20:00:24 -04:00
fregfile.sv	Synchronous reset in non-flop blocks	2021-10-26 08:30:35 -07:00
fsgn.sv	fpu cleanup	2021-07-24 14:59:57 -04:00
fsm_fpdiv_pipe.sv	Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking	2021-10-22 13:41:50 -05:00
fsm_fpdiv.sv	Clean up some signals - beautification onging	2021-10-14 17:12:00 -05:00
lzd_denorm.sv	fpu cleanup	2021-07-24 14:59:57 -04:00
rounder_denorm.sv	all fpu units use the unpacking unit	2021-07-28 23:49:21 -04:00
rounder_div.sv	Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.	2021-10-20 12:00:41 -05:00
sbtm_a0.sv	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
sbtm_a1.sv	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
sbtm_a2.sv	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
sbtm_a3.sv	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
sbtm_div.sv	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
sbtm_sqrt.sv	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
shifter_denorm.sv	fpu cleanup	2021-07-24 14:59:57 -04:00
unpacking.sv	lint warnings fixed	2021-10-12 09:45:02 -07:00