Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
02a1432c46
cvw/synthDC
History
Madeleine Masser-Frye 02a1432c46 updated synth makefile to change all relevant 
ram ranges to 1FF
2023-02-01 05:40:35 +00:00
..
ppa explanations and modifications for general ppa use 2022-07-09 03:24:47 +00:00
scripts Modified changes as follows 2023-01-28 19:33:00 -06:00
.synopsys_dc.setup Rolled back synth scripts to fff91ae commit before Madeleine's modifications to write config files; the modified version is failing right away with trouble copying configs 2022-08-24 00:09:16 +00:00
extractSummary.py Fixed config file writing for synthesis (#29) 2023-01-26 06:58:15 +02:00
Makefile updated synth makefile to change all relevant 2023-02-01 05:40:35 +00:00
README.md
wallySynth.py Fixed config file writing for synthesis (#29) 2023-01-26 06:58:15 +02:00

README.md

Synthesis for RISC-V Microprocessor System-on-Chip Design

This subdirectory contains synthesis scripts for use with Synopsys (snps) Design Compiler (DC). Synthesis commands are found in scripts/synth.tcl.

Example Usage make synth DESIGN=wallypipelinedcore FREQ=500

environment variables

DESIGN Design provides the name of the output log. Default is synth.

FREQ Frequency in MHz. Default is 500

CONFIG The Wally configuration file. The default is rv32e. Examples: rv32e, rv64gc, rv32gc

TECH The target standard cell library. The default is sky130. sky90: skywater 90nm TT 25C sky130: skywater 130nm TT 25C

SAIFPOWER Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif. The default is 0. 0: switching factor power analysis 1: RTL simulation driven power analysis.